DRAM refresh and charge leakage: Question bank — Hardware deep dive

The vocabulary here is all built in the parent note: a cell is charge on a capacitor, decay follows the RC time constant law $V (t) = V_{0} e^{- t / τ}$ , the reading device is a sense amplifier, and the timing names come from DDR SDRAM timing parameters. If any symbol looks unfamiliar, revisit the parent first.

Before the traps — three pictures you must have in your head

Everything below leans on four objects: the decay curve, the sense threshold line, the bitcell + sense-amp, and the refresh schedule. Let's draw each once so no trap uses an undrawn idea.

1 · The decay curve and the threshold line

Look at the figure. The burnt-orange curve is $V (t) = V_{0} e^{- t / τ}$ — the cell's voltage bleeding away. The plum dashed line is $V_{t h}$ . The moment the curve crosses that line is the retention time $t_{r e t}$ : after it, a stored 1 would be misread as 0.

Figure — DRAM refresh and charge leakage

Formula Where

$t_{r e t} = τ ln (V_{0} / V_{t h})$ actually comes from (the missing algebra) We want the time when the curve touches the threshold, so we set $V (t) = V_{t h}$ and solve for $t$ — that is literally asking "when does the falling voltage equal the decision line?": $V_{0} e^{- t_{r e t} / τ} = V_{t h}$ Step A — isolate the exponential (divide both sides by $V_{0}$ , because we want $e^{- t / τ}$ alone): $e^{- t_{r e t} / τ} = \frac{V _{t h}}{V _{0}}$ Step B — undo the exponential with $ln$ (the natural log is the only tool that cancels $e$ , turning an exponent into a plain multiplier): $- \frac{t _{r e t}}{τ} = ln \frac{V _{t h}}{V _{0}} = - ln \frac{V _{0}}{V _{t h}}$ Step C — multiply by $- τ$ to free $t_{r e t}$ : $t_{r e t} = τ ln \frac{V _{0}}{V _{t h}}$ With $V_{t h} = V_{0} /2$ the ratio is $2$ , so $t_{r e t} = τ ln 2 \approx 0.693 τ$ — the plum line in the figure sits exactly at that crossing.

The next figure walks the read/refresh in three frames, left to right: (a) the 1T1C bitcell holding charge, (b) the wordline opening the access transistor so the tiny cell capacitor shares its charge with the big bitline (a small voltage bump), and (c) the sense-amp latch amplifying that bump back to a full rail and driving it back into the cell — this last step is the restore/refresh.

3 · The refresh schedule — one symbol, three aliases reconciled

The figure shows the teal timeline: the full period $t_{R E F}$ split into $N$ equal slots, one REF pulse (orange, width $t_{R F C}$ = the busy time) per slot spaced $t_{R E F I}$ apart. Refresh overhead is the shaded orange busy-fraction, $t_{R F C} / t_{R E F I}$ .

4 · The two corner-case phenomena everyone forgets

True or false — justify

A read from DRAM leaves the row data intact just like a read from SRAM.

False — the DRAM read is destructive (the row dumps its charge onto the bitlines, frame (b) of figure 2), but the sense amps immediately re-drive and restore it in frame (c), so no data is lost. In SRAM the latch is never disturbed at all.

Refresh copies each row into a buffer and writes it back.

False — nothing is moved; activating the row lets the sense amp regenerate the full-voltage level in place on the same bitline (figure 2c). "Refresh" is regeneration, not relocation.

The 64 ms spec means every cell decays in exactly 64 ms.

False — 64 ms is set by the weakest cell in the whole chip (the left tail of the histogram in figure 4); most cells could safely hold their charge for seconds. The spec is a worst-case guarantee, not a typical decay time.

Because charge decays exponentially, a "1" turns into a "0" the instant any charge leaks.

False — a "1" is only mis-read once the curve falls below

V_{t h} \approx V_{0} /2

(the plum line in figure 1). Small leakage above that line is harmless; retention is

t_{r e t} = τ ln (V_{0} / V_{t h})

Hotter DRAM leaks faster, so JEDEC lengthens the refresh period when hot.

False — higher temperature means more leakage, smaller

R_{l e ak}

, smaller

τ

, so the period is halved to 32 ms above ~85°C to catch cells that now drain faster.

Distributed refresh and burst refresh give different retention guarantees.

False — both must cover all rows within the same

t_{R E F}

; they only differ in scheduling (evenly spread vs one long stall), not in how long any cell is allowed to sit unrefreshed.

A cell storing a logic 0 still needs to be refreshed.

Effectively false as "topping up" — a 0 is the absence of charge, so there's nothing to lose, but the row it lives in is still refreshed as a whole because refresh is row-granular and its neighbours storing 1s must be restored.

Doubling the capacitor size

C

doubles the retention time.

True to first order —

τ = R_{l e ak} C

, so with the same leak path a larger

C

holds more charge (

Q = C V

) and takes proportionally longer to fall to threshold. (In practice leakage paths change with geometry, but the

C

-dependence is real.)

SRAM never needs refresh because its cells don't leak.

False — SRAM transistors leak too, but the cross-coupled latch actively drives the stored value from the supply, continuously replenishing it, so no periodic external refresh command is needed.

A cell's retention time is a fixed constant you can measure once and trust forever.

False — variable retention time (VRT) means a single cell can randomly switch between a stronger and a weaker leakage state (figure 4), so a cell that tested "good" once may later drop into its weak state; profiling must allow safety margin for this.

Spot the error

"Retention time is

t_{r e t} = τ / ln 2

Error — it's

t_{r e t} = τ ln (V_{0} / V_{t h})

, which for

V_{t h} = V_{0} /2

τ ln 2 \approx 0.693 τ

, not

τ / ln 2

. The log multiplies, it doesn't divide (see the algebra in figure 1's formula box).

"Refresh overhead =

t_{R E F I} / t_{R F C}

Error — the ratio is inverted; overhead is busy time over interval,

t_{R F C} / t_{R E F I}

(the orange busy-fraction in figure 3). Busy 350 ns out of every 7.8 µs is the fraction lost, not the other way around.

"As chips add more rows at the same 64 ms, the per-REF interval

t_{R E F I}

stays fixed."

Error —

t_{R E F I} = t_{R E F} / N

, so more rows

N

at fixed

t_{R E F}

shrinks the interval between REFs, forcing them closer together and driving overhead up.

"The access transistor is fully off, so subthreshold leakage is zero."

Error — no real transistor is perfectly off; a small subthreshold current always flows, and it's one of the three main drain paths (with junction and dielectric leakage).

"Because

I = V / R_{l e ak}

, the leakage current stays constant as the cell discharges."

Error —

V

itself falls as the cell drains, so the current falls with it; that mutual dependence is exactly what produces the curved exponential decay of figure 1, not a straight line.

"A cell that survives a linear-model estimate of 12.5 s is guaranteed safe for 12.5 s."

Error — the linear constant-current model is optimistic and per-cell; the weakest cell (left tail of figure 4) may last only tens of ms, which is why the spec is 64 ms.

"Row-hammer only corrupts the row you keep activating."

Error — hammering a row leaks charge from its physical neighbours (figure 4), so the corrupted rows are the adjacent ones you never touched — that's what makes it a security problem.

Why questions

Why is DRAM called "dynamic" rather than "volatile"?

"Dynamic" refers to the charge continuously decaying (needing active refresh); "volatile" only means data is lost on power-off. DRAM is both, but the name captures the ongoing leakage behaviour of figure 1.

Why does an ordinary read count as a refresh for that row?

The read activates the whole row (figure 2b), the sense amp resolves and then re-drives each bitline back to full strength (2c) — restoring the charge — so the read inherently regenerates the row it touched.

Why do we set the sense threshold

V_{t h}

at roughly

V_{0} /2

instead of near

V_{0}

Half-way gives the maximum margin against noise for both a decaying 1 and a slightly-charged 0, so the sense amp can reliably distinguish them even after partial leakage.

Why does leakage rising exponentially with temperature matter more than a fixed leakage offset?

An exponential

\propto e^{- E_{a} / k T}

can cut retention by a large factor over a modest temperature rise, so the safe refresh period changes dramatically with heat — hence the 32 ms hot mode.

Why can refresh overhead climb toward 20% in large future chips?

More rows and bigger

t_{R F C}

per refresh, kept inside the same 64 ms, mean the bank is busy refreshing a larger fraction of every interval — overhead is

t_{R F C} / t_{R E F I}

(figure 3) and

t_{R E F I}

keeps shrinking.

Why does refresh happen at row granularity instead of cell-by-cell?

One activate dumps an entire row onto the bitlines simultaneously, and there's one sense amp per bitline restoring all cells at once — refreshing individual cells would be enormously slower and pointless.

Why does profiling retention (e.g. RAIDR) save power?

Since only the weakest cells need the tight 64 ms rate, cells known to hold charge far longer can be refreshed less often, cutting the number of REF commands and their energy — though it must budget for VRT (figure 4).

Edge cases

What happens to DRAM contents the moment power is removed?

Refresh stops, so every capacitor drains through its leak paths within a fraction of a second (curve of figure 1 running to zero) and the stored bits are lost — this is why DRAM is volatile.

A cell holds exactly the threshold voltage

V_{t h}

when the sense amp fires — what is read?

This is the metastable boundary; the outcome is unreliable, which is precisely why the spec keeps every cell comfortably above

V_{t h}

well before refresh, never letting it sit right at the plum line of figure 1.

Does a cell storing 0 (empty bucket) still risk being misread over time?

Generally no from leakage alone — an empty node can't lose charge it doesn't have, though it can slowly gain charge from junction/coupling, which is why 0-level restoration also matters at read.

If a bank is being continuously read across all its rows, does it still need explicit REF commands?

In principle every-row-read refreshes everything, but real access patterns are uneven, so the controller still issues REFs to guarantee the untouched rows are covered within

t_{R E F}

What is the limiting behaviour of

V (t) = V_{0} e^{- t / τ}

t \to \infty

It approaches 0 asymptotically (never exactly reaching it in the model, as figure 1 shows), which is why we define a finite retention time at the practical threshold rather than waiting for full drain.

Can refresh alone protect against row-hammer?

Only partially — a much faster refresh reduces the disturbance window, but the real fix is targeted refresh of victim neighbours (TRR) once a row is hammered too often, because plain periodic refresh may still be too slow for aggressive hammering.

Recall One-line takeaway (click to reveal)

Almost every DRAM trap comes from one of three truths: reads restore (not destroy for good), the spec is worst-cell not typical, and hotter means faster leak means shorter period — plus two real-world corners, VRT (retention wanders) and row-hammer (neighbours leak). Anchor every answer to those and the misconceptions dissolve.