Intuition The one-sentence pictureFlash memory stores bits as trapped electrons on an insulated gate. NOR wires cells so any single byte can be read instantly (great for code ); NAND wires cells in tight series strings to pack more bits per area (great for bulk data storage ).
Definition Floating-gate transistorA flash cell is a MOSFET with an extra floating gate buried between the control gate and the channel, wrapped in insulating oxide. Electrons pushed onto this floating gate stay there for years (it's electrically isolated), shifting the transistor's threshold voltage V t h V_{th} V t h
WHY it's non-volatile: the floating gate is surrounded by oxide, so trapped charge has nowhere to leak. No power needed to keep the data.
HOW a bit is encoded:
Charge on floating gate ⇒ high V t h V_{th} V t h 0 .
No charge ⇒ low V t h V_{th} V t h 1 (the "erased" state).
Intuition Threshold shift = the whole ideaThink of the floating gate as a tiny electron bucket sitting between the switch and the wire that flips it. Fill the bucket, and you need a much bigger push (control voltage) to flip the switch. We don't measure the electrons directly — we measure how hard it is to turn the transistor on .
Definition Program vs Erase mechanisms
Program (write 0): push electrons ONTO the floating gate. NAND uses Fowler–Nordheim (FN) tunnelling ; NOR classically uses channel hot-electron injection .Erase (back to 1): pull electrons OFF via FN tunnelling — done a whole block at a time.
Key asymmetry you must remember:
You can program individual pages (set 1→0 selectively).
You can only erase whole blocks (reset 0→1 in bulk).
You cannot flip a single bit 0→1 without erasing its entire block.
This is the defining constraint of flash and drives every flash filesystem / FTL design.
Each cell connects directly between a bit line and ground, in parallel . Any cell can be addressed and read on its own → true random access , fast reads, byte addressable.
Cells are connected in series into strings (typically 32–128+ cells) sharing one bit-line contact. This slashes contact/wiring overhead → smallest cell area, cheapest per bit, but you must read a whole page at once.
NOR: a bit line is pulled low if any selected cell conducts — like a wired-OR / NOR logic structure. Each cell is independently reachable ⇒ fast random read.NAND: to sense one cell in a string, all the others must be turned fully on (put in pass mode). The output depends on the whole series chain — like NAND logic. Fewer contacts ⇒ denser.
Density is further multiplied by storing several bits per cell (dividing the V t h V_{th} V t h
Definition Endurance (P/E cycles)Each program/erase cycle stresses the oxide (FN tunnelling wears it). Cells survive a limited number of Program/Erase (P/E) cycles before oxide degradation makes them unreliable. SLC ≫ MLC ≫ TLC ≫ QLC in endurance.
Intuition Wear leveling — why controllers existBecause blocks die after enough P/E cycles and you can only erase in blocks, a controller (the FTL , Flash Translation Layer) spreads writes across all blocks so no single block wears out early. This is why an SSD is not "just NAND."
Property
NOR NAND
Cell wiring
parallel (per-cell contact)
series strings
Cell size
~10 F 2 F^2 F 2
~4 F 2 F^2 F 2
Read
fast, random / byte
slower, page
Write/erase
slow
faster program, block erase
Random access
✅ execute-in-place (XIP)
❌ (must load page)
Cost / bit
high
low
Typical use
boot/firmware code (BIOS)
SSDs, USB, SD, phones
Bits/cell
usually SLC
SLC→QLC
Worked example 1 — Bits per cell from voltage levelsA TLC cell divides its V t h V_{th} V t h Why this step: each distinguishable level is one symbol; bits = log 2 \log_2 log 2 b = log 2 8 = 3 bits. b=\log_2 8 = 3 \text{ bits.} b = log 2 8 = 3 bits. Why it matters: 3 bits in one cell = 3× the raw capacity of SLC in the same silicon.
Worked example 2 — Density comparisonOn the same process, how many more NAND cells fit than NOR in the same area?
Why this step: ratio of areas per cell.
A NOR A NAND = 10 F 2 4 F 2 = 2.5 × . \frac{A_{\text{NOR}}}{A_{\text{NAND}}}=\frac{10F^2}{4F^2}=2.5\times. A NAND A NOR = 4 F 2 10 F 2 = 2.5 × . 3 × 3\times 3 × 7.5 × 7.5\times 7.5 ×
Worked example 3 — Why you can't edit one byte in placeA file uses 1 byte in a 4 KB page inside a 256 KB block. You change that byte.
Why this step: flash can only clear bits 0→1 by erasing a whole block.
Controller must: read the whole block → modify the byte in RAM → erase the block → rewrite it (or write to a fresh block and remap). One byte changed ⇒ a 256 KB erase/write. This "write amplification" is intrinsic to NAND.
Common mistake "Flash can rewrite any single bit like RAM."Why it feels right: reads are random-access, so writes seem like they should be too.
The fix: programming can only push bits 1→0 selectively; going 0→1 needs a block erase . Writes are page-granular, erases are block-granular. Never bit-granular.
Common mistake "NAND is just faster NOR."Why it feels right: NAND flash SSDs are super fast overall.
The fix: NOR has faster random reads and supports execute-in-place. NAND wins on density, cost, and sequential/page throughput , not random-byte latency. They target different jobs.
Common mistake "More bits per cell (QLC) is strictly better."Why it feels right: more capacity per cell sounds like pure win.
The fix: cramming more V t h V_{th} V t h
Common mistake "Charge on the gate = 1."Why it feels right: "storing something" feels like storing a 1.
The fix: convention is inverted — charged (high V t h V_{th} V t h 0 ; erased/empty = 1 . Erase resets to all 1s.
Recall Feynman: explain to a 12-year-oldImagine a light switch with a tiny bucket hidden inside it. Normally a small push flips the switch on. But if you fill the bucket with marbles (electrons), the switch gets "heavy" and needs a much bigger push — so at the normal push it stays OFF. That OFF means "0", empty bucket means "1". The marbles can't escape because the bucket is sealed, so it remembers even with the power off. NOR gives every switch its own wire so you can check any one instantly. NAND lines switches up in a row sharing one wire — cheaper and you fit way more, but to check one you have to force all the others on and read the whole row at once.
What structure stores the charge in a flash cell? The floating gate (an insulated gate between control gate and channel).
Charged floating gate reads as which bit? 0 (high threshold voltage, cell doesn't conduct).
Which is byte/random addressable for reads: NOR or NAND? NOR.
Which has smaller cell area (~4F²) and lower cost/bit? NAND.
Why can't you rewrite a single flash bit 0→1? 0→1 requires erasing, and erase happens only per whole block.
Write granularity vs erase granularity? Program = page; erase = block.
Mechanism NAND uses to program/erase? Fowler–Nordheim tunnelling.
Bits per cell for TLC and how derived? 3 bits, from log2(8 levels).
Why is QLC less durable than SLC? More voltage levels squeezed in → smaller margins → fewer P/E cycles and more errors.
What does the FTL do and why? Maps logical to physical blocks and wear-levels writes because blocks die after limited P/E cycles.
Typical use of NOR flash? Boot code / firmware (execute-in-place, e.g. BIOS).
What does "execute-in-place (XIP)" require and which flash supports it? Random byte read of code → NOR.
Mnemonic Remember the rolesN OR = N imble O n R andom reads → runs code. NAND = N eeds A N ice D ense pack → data storage. And "Ch arged = Ch ero (zero)": charge stored → 0.
MOSFET and threshold voltage — the physical device flash is built on.Non-volatile memory — flash's family (vs volatile RAM).Solid State Drives (SSD) — built from NAND + FTL controller.Fowler–Nordheim tunnelling — the program/erase physics.Wear leveling and write amplification — consequences of block erase.Memory hierarchy — where flash sits (below RAM, above disk).DRAM refresh — contrast: DRAM leaks & needs refresh; flash retains.
Channel hot-electron injection
Intuition Hinglish mein samjhoFlash memory ka core idea simple hai: ek transistor ke andar ek chhupa hua "floating gate" hota hai jismein electrons trap kar dete hain. Jab electrons stored hote hain, transistor ka threshold voltage badh jaata hai, matlab use ON karne ke liye zyada push chahiye — is state ko hum 0 padhte hain. Empty gate = 1 . Ye electrons sealed oxide ke andar phanse rehte hain, isliye power off hone par bhi data rehta hai — yahi non-volatile ka matlab hai.
Ab NOR vs NAND ka fark sirf wiring ka hai. NOR mein har cell alag wire se juda hota hai (parallel), isliye aap koi bhi ek byte turant random access se padh sakte ho — perfect for boot code/firmware jahan CPU ko directly code execute karna hota hai (execute-in-place). NAND mein cells ek series string mein pack hote hain, ek hi contact share karke — isse cell chhota (~4F²) aur sasta ban jaata hai, lekin aapko poora page ek saath padhna padta hai. Isliye SSD, pendrive, phone storage sab NAND use karte hain — density aur cost per GB ke liye.
Sabse important constraint yaad rakho: aap individual page program kar sakte ho (1→0), lekin bit ko 0→1 karne ke liye poora block erase karna padta hai. Bit-level rewrite possible nahi. Isi wajah se ek chhota sa byte change karne ke liye bhi controller ko poora block re-write karna pad sakta hai (write amplification), aur isiliye SSD mein FTL controller wear-leveling karta hai taaki koi block jaldi na mare. TLC/QLC mein ek cell mein zyada voltage levels (log 2 L \log_2 L log 2 L
