Exercises — Flash memory (NOR vs NAND)

WHAT: We check the reading convention. WHY: the bit is defined by whether the cell conducts at read voltage, not by "is there charge." Charge on gate ⇒ high $V_{th}$ ⇒ does NOT conduct ⇒ reads as 0. An empty (erased) gate ⇒ low $V_{th}$ ⇒ conducts ⇒ reads 1. Answer: 0.

• Parallel, per-cell contact → NOR (each cell independently reachable ⇒ fast random read).
• Series strings, shared contact → NAND (fewer contacts ⇒ denser, cheaper).

Read: byte/page (fine). Program: page. Erase: block (coarse). The one-way rule: you can clear bits $1\to 0$ per page, but restoring $0\to 1$ needs a whole-block erase. Never bit-granular. This asymmetry uses Fowler–Nordheim tunnelling.

WHY ${\log }_2$: each distinct level is one symbol; the number of bits needed to name $L$ symbols is ${\log }_{2}L$ (because $2^b$ symbols need $b$ bits). $b={\log }_{2}16=4\text{ bits.}$ Answer: 4 bits (that's the "Q" — quad — in QLC).

Invert $b={\log }_{2}L$: $L=2^b=2^3=8$ levels. Sanity check: SLC $2^1=2$, MLC $2^2=4$, TLC $2^3=8$, QLC $2^4=16$. ✔

WHAT: tightest packing = one line-width of active + one line-width of space in each direction. $A_{\text{NAND}}=\underset{x}{\underbrace{(2F)}}\times \underset{y}{\underbrace{(2F)}}=4F^2.$ NOR needs an extra contact + isolation per cell, inflating it to $\sim 10F^2$. Answer: $4F^2$. See the figure below.

WHY a ratio: cells-per-area is inversely proportional to area-per-cell, so divide the areas. $\frac{A_{\text{NOR}}}{A_{\text{NAND}}}=\frac{10F^2}{4F^2}=\mathrm{2.5.}$ Answer: $2.5\times$ more NAND cells in the same silicon.

WHY multiply: two independent multipliers — more cells and more bits each. $2.5(\text{cells})\times 3(\text{bits/cell})=7.5\times .$ Answer: $\approx 7.5\times$ more bits per area. This is why SSDs use TLC/QLC NAND, not NOR.

Order (most → least): SLC > MLC > TLC > QLC. Why: more bits/cell packs more $V_{th}$ levels into the same voltage window, so each level's margin shrinks. Oxide wear from Fowler–Nordheim tunnelling then pushes cells across those thin margins sooner — fewer usable P/E cycles. Tighter margins also demand heavier error correction. See Wear leveling and write amplification.

WHY the whole block: you cannot restore any $0\to 1$ bit without erasing its entire block — erase is block-granular. So the controller reads the 256 KB block into RAM, edits the byte, erases the block, rewrites all 256 KB. Physical work: $256\text{ KB}=256\times 1024=262144$ bytes written. $\text{Write amplification}=\frac{262144\text{ bytes physical}}{1\text{ byte logical}}=262144\times .$ Answer: 262144 bytes moved; amplification $=262144\times$. This intrinsic cost is exactly why the FTL and Wear leveling and write amplification exist.

WHY it's cheaper: by pointing the logical address at a new physical page it dodges the block erase entirely — it only pays for one page. Physical write: $4\text{ KB}=4\times 1024=4096$ bytes. $\text{Amplification}=\frac{4096}{1}=4096\times .$ Answer: 4096 bytes; amplification $=4096\times$. Still huge, but $64\times$ better than the naive block rewrite ($262144/4096=64$). The erase cost was deferred to background garbage collection.

(a) Boot firmware → NOR. Decisive reason: execute-in-place (XIP) needs true random/byte reads so the CPU fetches instructions directly. NOR's parallel per-cell wiring gives fast random reads; NAND must load a whole page first, so it can't XIP. (b) 128 GB user storage → NAND (TLC/QLC). Decisive reason: cost per bit. NAND's $\sim 4F^2$ series packing plus multi-bit cells give $\sim 7.5\times$ the bits/area of SLC NOR — the only economical way to reach 128 GB. Its slower random reads don't matter for bulk photo/app data. Fits the Memory hierarchy role of cheap bulk non-volatile store.

WHY multiply: perfect wear leveling means every byte of capacity can be rewritten once per P/E cycle, so total writes $=$ capacity $\times$ cycles. Capacity $=256\text{ GB}=256\times 10^9=2.56\times 10^{11}$ bytes (using decimal GB). $\text{Total writes}=2.56\times 10^{11}\times 1000=2.56\times 10^{14}\text{ bytes}=256\text{ TB.}$ Answer: $2.56\times 10^{14}$ bytes $=256$ TB (ideal). Why real drives fall short: write amplification is $>1$ (the L4 problem — a small logical write drags a bigger physical write), and wear leveling is imperfect, so the usable TBW is a fraction of this ceiling.