4.1.8 · D5Memory Technologies
Question bank — Flash memory (NOR vs NAND)
For the mechanisms named here (tunnelling, threshold voltage, wear), see Fowler–Nordheim tunnelling, MOSFET and threshold voltage, and Wear leveling and write amplification.
Notation & terms used on this page (build before you use)
Every trap below leans on the symbols, acronyms, and unit-words below. Read these once so no line surprises you.
True or false — justify
True or false: A flash cell with charge trapped on its floating gate reads as a 1.
False. Charge raises the threshold voltage so the transistor stays OFF at read voltage → that reads as 0. Empty gate = 1. The convention is inverted from "storing something = 1".
True or false: Flash is non-volatile because a battery keeps the charge topped up.
False. There is no battery. The floating gate is wrapped in insulating oxide, so trapped electrons have nowhere to leak — charge stays for years with zero power. See Non-volatile memory.
True or false: You can flip any single bit from 0 to 1 the same way you read it.
False. Going 0→1 (adding conduction, removing charge) requires an erase, and erase only happens a whole block at a time. Only 1→0 (programming) can be done at page granularity.
True or false: NAND is simply a faster version of NOR.
False. NOR wins on random-byte read latency and execute-in-place; NAND wins on density, cost per bit, and sequential throughput. They are optimised for different jobs, not the same job at different speeds.
True or false: A QLC cell is strictly better than an SLC cell because it holds more bits.
False. QLC (Quad-Level Cell) packs 4 bits by splitting the window into 16 levels, shrinking voltage margins → slower, fewer P/E (Program/Erase) cycles, heavier error correction. It's a capacity-vs-endurance/speed tradeoff.
True or false: NOR's parallel wiring makes each cell smaller than NAND's.
False. Parallel wiring gives every NOR cell its own bit-line contact plus isolation (, where is the feature size). NAND's series strings share one contact, reaching the ideal — NAND is the denser one.
True or false: Reading a single cell in a NAND string leaves the other cells in the string untouched.
False. To sense one cell, all the others in the string must be driven fully ON (pass mode) so current can flow through the whole series chain. You cannot isolate one cell electrically.
True or false: Fowler–Nordheim tunnelling wears out the oxide, which is why endurance is finite.
True. Each P/E (Program/Erase) cycle stresses the oxide via Fowler–Nordheim tunnelling; cumulative damage eventually leaks charge or shifts unreliably, ending the cell's usable life.
True or false: The floating gate is electrically connected to the control gate.
False. The floating gate is isolated — buried in oxide between the control gate and the channel. That isolation is exactly what makes stored charge permanent.
Spot the error
"To edit one byte, the controller just overwrites that byte in place." — What's wrong?
You can't clear the old bits (0→1) without erasing. The controller must read the whole block, modify in RAM, erase the block, and rewrite it — or write to a fresh block and remap. One byte → a whole-block write (write amplification).
"NAND cells are cheap because their transistors are physically simpler than NOR's." — What's wrong?
The transistors are essentially the same floating-gate MOSFETs. NAND is cheaper because series stringing removes per-cell contacts and isolation, not because the cell device is simpler.
"SLC stores 1 bit, so a cell with 8 threshold levels stores 8 bits." — What's wrong?
Bits = , not . With levels a cell stores bits (TLC, Triple-Level Cell), because each level is one distinguishable symbol, and bits address symbols.
"Because erase is done in blocks, writing must also be done in blocks." — What's wrong?
Programming (1→0) is done at page granularity, which is smaller than a block. Only erase (0→1) is block-granular. Mixing up the two granularities is the classic trap.
"NOR is byte-addressable for reads and writes, so it behaves like RAM." — What's wrong?
Only reads are byte-addressable. Writes still can't set 0→1 without an erase, and erases are block-wide. NOR is not RAM-like for writing.
"An SSD is just a slab of NAND chips, nothing more." — What's wrong?
An SSD also needs a controller running the FTL (Flash Translation Layer) for Wear leveling and write amplification, because blocks die after limited P/E cycles and can only be erased in bulk. See Solid State Drives (SSD).
Why questions
Why is NAND called "NAND" when it doesn't compute a logic NAND on your data?
Because sensing one cell requires the entire series string to conduct — output depends on all cells in series, structurally resembling NAND logic. The name is about wiring topology, not data logic.
Why does adding electrons to the floating gate make the cell harder to turn on?
The trapped negative charge partly cancels the control-gate field, so you need a larger control voltage to invert the channel — i.e. a higher threshold voltage . See MOSFET and threshold voltage.
Why does NOR support execute-in-place (XIP) but NAND does not?
NOR reads any byte directly with low latency, so a CPU can fetch instructions straight from it. NAND only delivers data a page at a time with sensing latency, so code must be copied to RAM first.
Why do more bits per cell (MLC→QLC) reduce endurance rather than just capacity?
More levels split the same range into narrower windows; tiny charge drift from oxide wear now crosses a level boundary, so the cell becomes unreliable after fewer P/E cycles.
Why does changing one byte in NAND often cause far more than one byte of physical writing?
Erase granularity is a whole block, so the surrounding valid data must be rewritten too. This inflation of physical writes vs logical writes is write amplification.
Why can flash forget data even with no power, unlike DRAM's constant need for refresh?
Flash charge sits on an isolated gate and only leaks slowly over years, so no refresh is needed. DRAM stores charge on a leaky capacitor that drains in milliseconds — contrast with DRAM refresh.
Edge cases
Edge case: A fresh, never-written NAND block — what value do all its cells read?
All 1s. Erase is the reset-to-1 operation, so an erased/empty block is all-1s; programming only ever pulls selected bits down to 0.
Edge case: What happens if you try to program a bit that is already 0?
Nothing useful — it stays 0. Programming can only drive 1→0; a bit already at 0 can't be "un-programmed" without a block erase.
Edge case: A single cell in a NAND string is defective (stuck non-conducting) — can you still read its neighbours?
No. A broken series link blocks current through the whole string, so every cell sharing that string becomes unreadable — the controller must remap around it.
Edge case: Two adjacent QLC threshold levels drift toward each other over years of retention — what fails first?
Read correctness. The sense circuit can no longer tell the two levels apart, causing bit errors that error-correction must absorb before the cell is retired. Fewer levels (SLC) tolerate far more drift.
Edge case: You repeatedly write to the same logical address on an SSD — which physical blocks wear out?
Ideally none prematurely, because the FTL (Flash Translation Layer) performs wear leveling, spreading writes across many physical blocks so no single block absorbs all the P/E cycles.