Visual walkthrough — Flash memory (NOR vs NAND)

This is the picture-derivation behind the parent topic. If any word below feels unfamiliar, it gets defined the moment it appears.

---

Step 1 — What is $F$? The smallest thing the factory can draw

WHAT we did: named the fundamental unit of length on a chip.

WHY this and not nanometres directly: if we count everything in "pencil strokes" $F$, the shape of a memory cell has a size that does not depend on which factory built it. A $4F^2$ cell is $4F^2$ whether $F=90\text{ nm}$ or $F=14\text{ nm}$. It makes cells comparable across generations.

PICTURE: below, one stroke of width $F$, and the smallest possible gap (also $F$) beside it. You literally cannot squeeze two lines closer than $F$ apart, or the light bleeds and they merge.

---

Step 2 — One cell needs a line AND a gap, in both directions

WHAT we did: set the ideal packing rule — active region $F$, isolation gap $F$.

WHY a gap at all: two transistors touching would leak current into each other (the switches would interfere). The gap is the minimum insulation, and the minimum printable gap is exactly $F$.

PICTURE: the pitch (repeat distance) of a row of cells is $F+F=2F$. Same going up. So the smallest a cell footprint can ever be is $2F$ across by $2F$ tall.

$A_{\text{ideal}}=\underset{\text{width: line}+\text{gap}}{\underbrace{(2F)}}\times \underset{\text{height: line}+\text{gap}}{\underbrace{(2F)}}=4F^2.$

Every term: the first $2F$ is one horizontal pitch (a wire plus its gap); the second $2F$ is one vertical pitch; multiplied, they give the area of the single smallest possible cell — the $4F^2$ ideal.

---

Step 3 — Why NOR can't reach $4F^2$: the contact tax

WHAT we did: added the thing NOR cannot avoid — a private contact per cell.

WHY it costs area: a contact needs its own stroke of width, its own surrounding gap so it doesn't short to neighbours, plus extra isolation. Counting strokes, a NOR cell spreads to roughly $\sim 4$–$5$ strokes one way and $2$ the other:

$A_{\text{NOR}}\approx \underset{\text{cell}+\text{contact}+\text{isolation}}{\underbrace{(5F)}}\times \underset{\text{pitch}}{\underbrace{(2F)}}=10F^2.$

The first factor $5F$ is inflated by the contact and its isolation; the second $2F$ is still one pitch. Result: $10F^2$, about $2.5\times$ the ideal.

PICTURE: two NOR cells, each with its own fat contact plug eating space between them.

---

Step 4 — Why NAND reaches $4F^2$: share one contact across many cells

WHAT we did: amortised the contact tax over a long chain.

WHY it works: inside the string, neighbouring cells simply touch source-to-drain — no gap, no contact between them. Only the two ends of the string touch the outside world. So per cell you're back to just line + gap = $2F\times 2F$.

PICTURE: a NAND string of beads sharing end-contacts; the per-cell box shrinks back to the ideal $2F\times 2F$.

$A_{\text{NAND}}\approx 4F^2,\frac{A_{\text{NOR}}}{A_{\text{NAND}}}=\frac{10F^2}{4F^2}=\mathrm{2.5.}$

The ratio $2.5$ says: on identical silicon, 2.5 NAND cells fit in the space of one NOR cell. Each symbol: numerator = NOR area, denominator = NAND area, both in $F^2$ so the $F^2$ cancels — a pure count.

---

Step 5 — The second multiplier: bits per cell from voltage levels

WHAT we did: turned "how full is the bucket" into a number of distinct symbols $L$.

WHY ${\log }_2$ and not just $L$: bits count yes/no questions. With $L$ equally-likely levels, the number of binary questions needed to pin one down is ${\log }_{2}L$. Two levels $\Rightarrow$ 1 question $\Rightarrow$ 1 bit; four levels $\Rightarrow$ 2 questions $\Rightarrow$ 2 bits. That is exactly the definition of ${\log }_2$: "2 to what power gives $L$?"

$b={\log }_{2}L\text{bits per cell.}$

Here $b$ is bits stored, $L$ is the count of usable voltage windows, and ${\log }_2$ converts a symbol count into a bit count.

PICTURE: the $V_{th}$ axis sliced into 2, 4, 8, 16 windows (SLC→QLC). More slices = more bits, but the gaps between windows shrink — the source of QLC's fragility.

Name	$L$	$b={\log }_{2}L$
SLC	2	1
MLC	4	2
TLC	8	3
QLC	16	4

---

Step 6 — Multiply the two effects: total density advantage

WHAT we did: combined the geometric win with the level win.

WHY multiply (not add): "2.5× as many cells" and "3× as many bits in each cell" compound — like doubling the number of shelves and tripling the books per shelf.

$\text{bits per area}\propto \underset{\text{area ratio (Step 4)}}{\underbrace{2.5}}\times \underset{\text{TLC vs SLC (Step 5)}}{\underbrace{3}}=\mathrm{7.5.}$

So TLC NAND stores about $7.5\times$ more bits per unit area than SLC NOR — exactly the parent's claim, now derived from strokes and slices.

PICTURE: a bar showing the two multipliers stacking into the $7.5\times$ total.

---

Step 7 — The degenerate cases (never leave a gap)

• $L=1$ (one level): $b={\log }_{2}1=0$ bits. A cell that can only ever be in one state stores nothing — you can't distinguish anything. The formula correctly returns 0.
• Zero-length string (NAND with 1 cell): if a "string" holds only one cell, both end-contacts belong to it — it degenerates back into the NOR case, no sharing, area balloons to $\sim 10F^2$. The $4F^2$ ideal needs a long string to amortise contacts.
• Ideal vs real $F$: $4F^2$ is a floor, never quite reached — real cells add margin. So published numbers ($\sim 4$–$6F^2$) sit slightly above the ideal; the derivation gives the limit, not the exact fab number.
• Reading a NAND cell: to sense one cell you must turn all other cells in its string fully on (pass-through). If even one neighbour is stuck, the whole string reads wrong — the price of sharing wires. This is why NAND reads a whole page, never a lone byte.

PICTURE: the $L=1$ collapse (zero bits) and the single-cell string collapse (back to NOR area) side by side.

---

The one-picture summary

Everything on one canvas: a pencil-stroke of width $F$ → the $2F\times 2F$ ideal cell → NOR's contact tax pushing it to $10F^2$ → NAND's shared string pulling it to $4F^2$ → the $V_{th}$ axis sliced into $L$ levels giving ${\log }_{2}L$ bits → the two multipliers compounding to $7.5\times$.

Recall Feynman retelling — the whole walkthrough in plain words

The factory can only draw lines a certain thinness — call one stroke $F$. The tiniest possible memory cell is one stroke of stuff plus one stroke of empty gap, in both directions: $2F$ by $2F$, which is $4F^2$. But NOR wiring insists every cell get its own little metal plug (a contact) with insulation around it, and that plug fattens the cell to about $10F^2$. NAND's clever trick is to string a hundred-plus cells in a row and let the whole row share just two end-plugs — so per cell you're back down to the ideal $4F^2$, about 2.5 times denser than NOR. Then a second trick: instead of "bucket full or empty" (1 bit), you fill the bucket to several precise levels; $L$ levels store ${\log }_{2}L$ bits, so TLC's 8 levels give 3 bits. Both tricks multiply: 2.5× smaller cells times 3× the bits each is about 7.5× more storage in the same chip. Edge checks: one level stores zero bits (nothing to tell apart); a "string" of one cell loses the sharing and bloats back to NOR size; and $4F^2$ is a floor real chips only approach, never beat.

Recall Quick self-test

Why is NAND denser than NOR at the cell level? ::: NOR needs a private contact + isolation per cell (~10F²); NAND shares end-contacts across a long series string, hitting the ideal ~4F². Why do bits per cell use ${\log }_{2}L$ and not $L$? ::: Bits count binary yes/no questions; ${\log }_{2}L$ is how many such questions distinguish one of $L$ equally-likely levels. What does the $4F^2$ ideal require to actually hold? ::: A long series string so the two end-contacts are amortised to near-zero per cell; a 1-cell string collapses back to NOR area.