Flash memory (NOR vs NAND): Worked examples — Hardware deep dive

This page drills the counting and constraint maths behind Flash memory (NOR vs NAND): bits-per-cell, density ratios, write-amplification arithmetic, endurance budgets, and the "you can't flip one bit" corner cases. We build each number from zero — no formula is used before it is earned.

Before we start, three plain-word reminders (each one is a "symbol" we will reuse):

The scenario matrix

Every flash-arithmetic problem you will meet falls into one of these cells. The worked examples below are tagged with the cell they cover.

#	Case class	Degenerate / edge form	Example
A	Bits from levels ( $b = lo g_{2} L$ )	$L = 2$ (SLC, one bit), $L$ not a power of 2	Ex 1, Ex 2
B	Density ratio (NOR vs NAND area)	equal process $F$	Ex 3
C	Combined density (area × bits/cell)	SLC-NOR vs QLC-NAND extreme	Ex 4
D	Write amplification (edit one byte)	1 byte changed → whole block	Ex 5
E	Endurance budget (writes before wear-out)	worst case, no wear leveling	Ex 6, Ex 7
F	Real-world word problem (SSD lifetime)	daily writes over years	Ex 7
G	Exam twist / trap (charge = 0, not 1)	zero charge = erased = 1	Ex 8

Worked examples

Worked example Ex 4 — Cell C: combined density, the extreme corners

Compare SLC NOR (worst density) against QLC NAND (best density) on the same process. How many raw bits per unit area does NAND win by?

Forecast: multiply the area advantage by the bits-per-cell advantage.

Area advantage (from Ex 3): $2.5 \times$ more cells. Why this step? Sets how many cells share the silicon.
Bits-per-cell advantage. SLC $= 1$ bit, QLC $= lo g_{2} 16 = 4$ bits. Ratio $= 4/1 = 4$ . Why this step? $2^{4} = 16$ so QLC stores 4 bits — four times SLC's payload per cell.
Multiply the two independent gains. $2.5 \times 4 = 10$ . Why this step? Cells-per-area and bits-per-cell are separate factors, so total bits-per-area is their product. $NAND advantage = 2.5 \times 4 = 10 \times .$

Verify: cross-check with the parent's Ex 2 (TLC gave $2.5 \times 3 = 7.5 \times$ ). QLC's extra bit lifts $7.5$ to $2.5 \times 4 = 10$ — consistent and larger, as expected. ✅

Worked example Ex 5 — Cell D: write amplification, changing one byte

A 256 KB block holds 4 KB pages. You change 1 byte. How many bytes must actually be erased+rewritten in the naive "read-modify-write the block" scheme, and what is the write-amplification factor (WAF)?

Forecast: you touched 1 byte — but flash erases whole blocks. Guess how many real bytes move.

Recall the constraint. You can set bits $1 \to 0$ per page, but $0 \to 1$ needs a block erase. Why this step? Editing a byte in place may need some $0 \to 1$ flips, which are impossible without erasing the enclosing block.
Count block size in bytes. $256 KB = 256 \times 1024 = 262144$ bytes. Why this step? The whole block is read to RAM, erased, and rewritten.
Compute WAF. $WAF = \frac{physical bytes written}{logical bytes changed} = \frac{262144}{1}$ . Why this step? WAF measures how much the drive actually writes per byte you asked to change — the intrinsic tax of NAND. $WAF = \frac{262144}{1} = 262144.$

Verify: in the figure, the single red byte forces the entire grey block to cycle. Sanity: WAF $\geq 1$ always (you write at least what you asked); here it is enormous, which is exactly why controllers batch writes and remap instead of editing in place. ✅

Worked example Ex 7 — Cells E+F: real-world SSD lifetime word problem

A 512 GB TLC SSD rated at $3, 000$ P/E cycles has ideal wear leveling (writes spread perfectly across all blocks). You write $50$ GB per day. Ignoring write amplification, how many years until the flash wears out?

Forecast: total lifetime writes = capacity × cycles. Then divide by daily rate.

Total writable bytes over life. $TBW = capacity \times P/E cycles = 512 \times 3000 = 1, 536, 000$ GB. Why this step? Perfect wear leveling means every block can be cycled its full 3000 times, so the whole drive absorbs capacity × cycles of writes.
Days of life. $\frac{1 , 536 , 000 GB}{50 GB/day} = 30, 720$ days. Why this step? Lifetime writes divided by write rate gives elapsed time; the GB units cancel, leaving days.
Convert to years. $\frac{30720}{365} \approx 84.16$ years. Why this step? $365$ days = 1 year converts the answer to a human scale. $t \approx 84.2 years.$

Verify: units check — $\frac{GB}{GB/day} = days$ , then $/ (days/year) = years$ ✅. The comfortably-long life is because wear leveling exists; drop it (Ex 6 world) and one block dies in days. Real drives shrink this via write amplification (WAF > 1). See Solid State Drives (SSD).

Worked example Ex 8 — Cell G: the inverted-convention exam trap

Trap question: "A cell has no charge on its floating gate. It reads as bit ___, and its threshold voltage $V_{t h}$ is (high / low)?"

Forecast: intuition screams "empty = nothing = 0". Resist it.

Apply the encoding rule. No charge ⇒ low $V_{t h}$ ⇒ cell conducts at read voltage ⇒ reads 1. Why this step? Bits are read by whether the transistor turns on, not by "is there stuff inside." (See MOSFET and threshold voltage.)
State the erased convention. Erasing a block pulls charge off → all cells become $V_{t h}$ -low → all read $1$ . Why this step? "Erased = all ones" is the standard, and programming later flips selected $1 \to 0$ . $no charge \Rightarrow low V_{t h} \Rightarrow reads 1.$

Verify: consistent with the parent's mistake callout ("charged = 0, erased/empty = 1"). Charge count 0 ↔ bit 1 — the convention is deliberately inverted. ✅

Recall Quick self-test

A cell resolves 5 clean levels — how many whole bits? ::: $⌊ lo g_{2} 5 ⌋ = 2$ bits (since $2^{2} = 4 \leq 5 < 8 = 2^{3}$ ). Same-process area ratio NOR:NAND with $10 F^{2}$ and $4 F^{2}$ ? ::: $2.5 \times$ . Change 1 byte in a 256 KB block, naive scheme — bytes rewritten? ::: $262144$ (the whole block). Empty floating gate reads as which bit? ::: 1 (low $V_{t h}$ , conducts).