Floating gate transistor operation

WHAT is it?

The stack, bottom-to-top:

Channel / substrate (silicon, with source & drain).
Tunnel oxide (thin, ~8–10 nm) — electrons cross this to reach the FG.
Floating gate (poly-silicon, isolated) — the charge store.
Inter-poly / control oxide (thicker) — blocks charge from escaping upward.
Control gate (the terminal you actually drive).

Figure — Floating gate transistor operation

WHY does stored charge encode a bit? (Derive the threshold shift)

WHY: In an ordinary MOSFET, the channel turns on when the control-gate voltage exceeds the threshold $V_T$ . If we can change $V_T$ at will and have it stay changed, we have a memory.

HOW — derive $\Delta V_T$ from charge conservation.

Treat the floating gate as the middle plate of two series capacitors:

$C_{CG}$ = capacitance between control gate and floating gate.
$C_{FG}$ = capacitance between floating gate and channel/substrate (and source/drain).

The floating-gate potential $V_{FG}$ is set by capacitive division of the control voltage $V_{CG}$ plus whatever charge $Q_{FG}$ sits on the gate. By charge on the FG node:

$Q_{FG} = C_{CG}(V_{FG}-V_{CG}) + C_{FG}(V_{FG}-V_{ch})$

Solve for $V_{FG}$ (take $V_{ch}=0$ reference):

$V_{FG} = \underbrace{\frac{C_{CG}}{C_{CG}+C_{FG}}}_{\text{coupling ratio } \alpha_G}\,V_{CG} + \frac{Q_{FG}}{C_{CG}+C_{FG}}$

Why this step? The FG is floating, so its voltage is not driven directly — it is whatever the capacitor network + trapped charge force it to be. That is exactly a capacitive divider with an extra charge term.

The device conducts when $V_{FG}$ reaches the intrinsic threshold $V_{T0}$ . Setting $V_{FG}=V_{T0}$ and solving for the control-gate voltage we must apply:

$V_{T,\text{observed}} = \frac{V_{T0}}{\alpha_G} - \frac{Q_{FG}}{C_{CG}}$

Why the sign: electrons on the FG electrostatically oppose the control gate's field, so you need a bigger $V_{CG}$ to invert the channel.

HOW do electrons get on/off the isolated gate?

They can't flow through wires (it's isolated!), so we use quantum & high-field mechanisms across the thin tunnel oxide:

Definition Programming mechanisms

Fowler–Nordheim (FN) tunneling: a strong field ( $\sim 10\text{ MV/cm}$ ) thins the oxide energy barrier enough for electrons to quantum-tunnel through. In floating-gate NAND Flash, FN tunneling is used for the erase operation (and, in some designs, for programming too), moving charge across the whole tunnel oxide with very low current.
Channel Hot-Electron (CHE) injection: electrons in the channel are accelerated by drain voltage, gain enough energy to jump over the oxide barrier onto the FG. Used to program NOR Flash, and it is also the standard programming mechanism for floating-gate NAND cells. Faster injection but higher power.

Rule of thumb for FG NAND: program = channel hot-electron injection, erase = Fowler–Nordheim tunneling. (NOR: program = CHE, erase = FN.)

Reading the bit: apply a read voltage $V_{read}$ between the two thresholds. If the cell conducts → it's the erased/low- $V_T$ state (1); if it stays off → programmed/high- $V_T$ state (0).

$V_{T}(\text{erased}) < V_{read} < V_{T}(\text{programmed})$

Worked example Estimating

$\Delta V_T$ — Why each step? Let $C_{CG}=1\text{ fF}=1\times10^{-15}\text{ F}$ and we inject $N=1000$ electrons.

$Q_{FG} = -N q = -1000 \times 1.6\times10^{-19} = -1.6\times10^{-16}\text{ C}$ . Why negative: electrons carry negative charge.
$\Delta V_T = -Q_{FG}/C_{CG} = -(-1.6\times10^{-16})/(1\times10^{-15}) = +0.16\text{ V}$ .
Why it matters: just a thousand electrons shift the threshold by a measurable 160 mV — that's why the cell is so small yet reliable... until oxide leakage lets those few electrons escape (data loss).

Multi-Level Cells (the 80/20 payoff idea)

Because $\Delta V_T$ is continuous in $Q_{FG}$ , we can store more than one $V_T$ level per cell. 4 distinct charge levels → 2 bits (MLC); 8 levels → 3 bits (TLC); 16 → 4 bits (QLC). Why the tradeoff: more levels = narrower voltage windows = less error margin = slower, less durable. This single idea explains most of modern SSD capacity/endurance tradeoffs.

Common mistakes

Forecast-then-Verify

Answer: smaller, because $\Delta V_T = -Q_{FG}/C_{CG}$ is inversely proportional to $C_{CG}$ . Bigger coupling capacitance "dilutes" the same trapped charge into a smaller voltage swing — a real design tension between good control-gate coupling ( $\alpha_G$ ) and large sensing margin.

Flashcards

What physically distinguishes a floating gate transistor from an ordinary MOSFET?

An extra electrically-isolated conducting gate (the floating gate) buried in the oxide between the control gate and the channel.

Why is the floating gate transistor non-volatile?

The floating gate is surrounded by insulating oxide, so trapped charge has nowhere to leak and is retained without power.

State the threshold shift due to trapped charge.

\Delta V_T = -Q_{FG}/C_{CG}

Does adding electrons to the FG raise or lower the observed threshold?

Raises it (negative charge opposes the control gate, needing higher

V_{CG}

to invert the channel).

Which state (programmed/erased) has the higher threshold?

Programmed (electrons stored) has the higher

V_T

; erased has the lower

V_T

In floating-gate NAND, which mechanism programs and which erases?

Program = channel hot-electron injection; Erase = Fowler–Nordheim tunneling.

Name the two charge-transfer mechanisms and their physics.

Fowler–Nordheim tunneling (electrons quantum-tunnel through the thinned oxide barrier under high field) and Channel Hot-Electron injection (accelerated channel electrons jump over the barrier).

How is a cell read without disturbing its data?

Apply a read voltage between the erased and programmed thresholds; sense current. It's too low to tunnel/inject charge, so it's non-destructive.

Define the gate coupling ratio

\alpha_G

\alpha_G = C_{CG}/(C_{CG}+C_{FG})

; the fraction of control-gate voltage that appears on the floating gate.

Why do TLC/QLC cells store more bits but wear out faster?

V_T

levels packed into the same window → narrower margins → more errors and less endurance.

Recall Feynman: explain to a 12-year-old

Imagine a light switch that is sticky. Normally you push it and it turns the light on. But this switch has a tiny secret pocket inside where you can trap some invisible "grumpy dust" (electrons). When grumpy dust is in the pocket, the switch fights you — you have to push much harder to turn the light on. When the pocket is empty, the switch is easy. The trick: the pocket is sealed so tight that the dust stays for years, even if you unplug everything. So we look at "is this switch easy or hard to flip?" and that tells us whether we stored a 1 or a 0. That's a memory cell!

Connections

MOSFET operation — the FG cell is just a MOSFET with a modified gate; understand $V_T$ first.
Fowler-Nordheim tunneling — the quantum mechanism that erases NAND cells.
Channel hot-electron injection — the mechanism that programs FG NAND (and NOR).
NAND vs NOR Flash architecture — how FG cells are wired into arrays.
Multi-level cell (MLC TLC QLC) — exploiting continuous $\Delta V_T$ .
Charge trap flash and 3D NAND — the successor that replaces the conductive FG with an insulating trap layer.
EEPROM and EPROM — earlier devices using the same principle.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, floating gate transistor basically ek normal MOSFET hi hai, bas ek extra gate uske andar oxide ke beech chhupa hua hota hai — usko "floating gate" kehte hain kyunki wo kisi wire se connect nahi hota, poori tarah insulator se ghira hota hai. Isi wajah se agar hum ismein kuch electrons daal dein, toh wo bahar nahi ja sakte, saalon tak wahin trapped rehte hain. Power off ho jaaye tab bhi data safe — isliye Flash/SSD non-volatile hote hain.

Ab magic ye hai: jab floating gate par electrons trapped hote hain, wo negative charge control gate ki field ko oppose karta hai. Matlab transistor ko ON karne ke liye tumhe zyada voltage lagana padega — threshold voltage $V_T$ badh jaata hai. Formula simple hai: $\Delta V_T = -Q_{FG}/C_{CG}$ . Charge negative (electrons) → $V_T$ up → ye "programmed" state = 0. Electrons nikaal do → $V_T$ neeche → "erased" = 1.

Electrons andar/bahar kaise jaate hain jab gate isolated hai? Do tarike: channel hot-electron injection (channel mein electron ko drain voltage se tez karo, itni energy mil jaati hai ki oxide ki wall ke upar se kood jaata hai) — ye floating-gate NAND aur NOR dono ko program karta hai. Aur Fowler-Nordheim tunneling (bahut strong field lagao, electron quantum-mechanically oxide ke through nikal jaata hai) — ye NAND ka erase karta hai. Simple rule: program = hot-electron injection, erase = FN tunneling. Reading ke liye ek $V_{read}$ lagate hain jo erased aur programmed threshold ke beech ho — current aayi toh 1, nahi toh 0, aur ye voltage itni chhoti hoti hai ki charge disturb nahi hota.

Yaad rakho: "Electrons Elevate threshold" aur "Push in Hot, Tunnel out." MLC/TLC/QLC ka idea bhi yahin se — kyunki $V_T$ continuously charge par depend karta hai, ek hi cell mein multiple charge levels store karke 2, 3, ya 4 bits daal sakte hain. Jitne zyada levels, utna kam margin, utni kam durability — SSD ki saari capacity-vs-endurance tradeoff isi ek baat se samajh aa jaati hai.

WHAT is it?

WHY does stored charge encode a bit? (Derive the threshold shift)

HOW do electrons get on/off the isolated gate?

Multi-Level Cells (the 80/20 payoff idea)

Common mistakes

Forecast-then-Verify

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Memory Technologies

Connections