Floating gate transistor operation: Worked examples

Before we start, one full re-cash of the notation so a first-time reader can follow line one.

Definition The symbols we will reuse

$Q_{F G}$ — the total electric charge trapped on the floating gate, measured in coulombs (C). Electrons make it negative.
$q$ — the charge of ONE electron's worth of magnitude, $q = 1.6 \times 1 0^{- 19} C$ . So $N$ electrons give $Q_{F G} = - N q$ (minus sign because electrons are negative).
$C_{C G}$ — the capacitance between the control gate and the floating gate, in farads (F). Bigger $C_{C G}$ = the two plates couple more strongly. Typical: $\sim 1 fF = 1 0^{- 15} F$ .
$C_{F G}$ — the capacitance between the floating gate and the channel/substrate below it, also in farads (F). It is the other plate-pair sandwiching the floating gate: the control gate sits above it (giving $C_{C G}$ ), the channel sits below it (giving $C_{F G}$ ). We use it in Example 8 to build the coupling ratio.
$V_{T}$ — the threshold voltage: the control-gate voltage at which the channel finally switches ON. Higher $V_{T}$ = harder to turn on.
$Δ V_{T}$ — how much $V_{T}$ moved because of the trapped charge, relative to the empty-gate (erased) baseline.

The scenario matrix

Every problem this topic can throw is one of these case-classes. The examples below hit each cell.

#	Case class	What is degenerate/limiting about it	Example
A	Negative charge (electrons injected → programmed)	ordinary "sign of charge" case	Ex 1
B	Positive charge (net holes / over-erase)	opposite sign — $V_{T}$ goes below baseline	Ex 2
C	Zero charge (fully erased, $Q_{F G} = 0$ )	degenerate input, $Δ V_{T} = 0$	Ex 3
D	The read decision (does it conduct?)	the three sub-cases: below / between / above	Ex 4
E	Multi-level packing (many $Q$ levels)	how fine can we slice the charge axis?	Ex 5
F	Design-parameter sweep ( $C_{C G}$ changes)	limiting behaviour as $C_{C G} \to$ large/small	Ex 6
G	Leakage over time (retention, real world)	charge slowly drains → $Δ V_{T}$ decays	Ex 7
H	Exam twist (coupling ratio $α_{G}$ + intrinsic $V_{T 0}$ )	full observed-threshold formula, not just the shift	Ex 8

Example 1 — Case A: electrons injected (programmed cell)

Worked example Program a cell with 1000 electrons

A cell has $C_{C G} = 1 fF = 1 \times 1 0^{- 15} F$ . We inject $N = 1000$ electrons onto the floating gate. By how much does the threshold move, and in which direction?

Forecast: Electrons are negative. Will $V_{T}$ go up or down? Guess a sign before reading on.

Step 1 — Convert electron count to charge. $Q_{F G} = - N q = - 1000 \times 1.6 \times 1 0^{- 19} = - 1.6 \times 1 0^{- 16} C$ Why this step? The engine formula eats charge in coulombs, not a count. The minus sign is physics: an electron carries negative charge.

Step 2 — Feed it to the engine. $Δ V_{T} = - \frac{Q _{F G}}{C _{C G}} = - \frac{- 1.6 \times 1 0 ^{- 16}}{1 \times 1 0 ^{- 15}} = + 0.16 V$ Why this step? Two minus signs cancel → a positive shift. Positive means the threshold rose: you now need $0.16 V$ more on the control gate to turn the cell on. That is exactly the "harder to turn on = programmed = stored 0" behaviour.

Verify: Units: $C / F = V$ ✓. Sign matches intuition — negative charge on the gate repels the control field. Magnitude ( $160 mV$ ) is large enough for a sense amp to distinguish. Forecast check: $V_{T}$ went up.

Example 2 — Case B: net positive charge (over-erase)

Worked example The cell has been erased too hard

During erase, FN tunneling pulled electrons off the gate — but too many left, leaving the gate with a net positive charge equivalent to $500$ missing electrons. Same $C_{C G} = 1 fF$ . Find $Δ V_{T}$ relative to the neutral baseline.

Forecast: With positive trapped charge instead of negative, does the shift flip to the other side of baseline? Guess the sign.

Step 1 — Charge of a positively-charged gate. $Q_{F G} = + N q = + 500 \times 1.6 \times 1 0^{- 19} = + 8.0 \times 1 0^{- 17} C$ Why this step? "500 electrons missing" leaves 500 units of positive charge behind. Now $Q_{F G} > 0$ — the opposite sign to Example 1.

Step 2 — Engine. $Δ V_{T} = - \frac{+ 8.0 \times 1 0 ^{- 17}}{1 \times 1 0 ^{- 15}} = - 0.08 V$ Why this step? Positive charge on the gate helps the control field, so the channel turns on too easily — $V_{T}$ drops below baseline. This is the dreaded over-erase: the cell can conduct even at $0 V$ , corrupting reads of neighbouring cells (a real failure mode NAND designers guard against).

Verify: Sign is negative, mirror-image of Example 1's positive shift — consistent with the linear engine $Δ V_{T} \propto - Q$ . Units $C / F = V$ ✓.

Example 3 — Case C: zero charge (the degenerate baseline)

Worked example What is the shift of a perfectly erased cell?

A fresh, perfectly erased cell has no net charge: $Q_{F G} = 0$ . What is $Δ V_{T}$ ?

Forecast: With nothing trapped, what should the shift be?

Step 1 — Plug zero in. $Δ V_{T} = - \frac{0}{C _{C G}} = 0 V$ Why this step? We must always check the degenerate input — the case where the machine is fed "nothing." Here the answer is clean: no charge, no shift. The observed threshold equals the intrinsic threshold (up to the coupling ratio, see Ex 8).

Step 2 — Why this is the reference point. Every $Δ V_{T}$ we quote is measured from this state. It is the "erased / stores 1 / low- $V_{T}$ " corner. Without a well-defined zero, "shift by $+ 0.16 V$ " would be meaningless.

Verify: $0/ C_{C G} = 0$ for any non-zero $C_{C G}$ ✓. This is the anchor the other examples move away from.

Example 4 — Case D: the read decision (all three sub-cases)

Two new symbols enter here, so we name them before use.

The figure below is a threshold number line: the horizontal axis is $V_{T}$ in volts, the three coloured tick marks are the three cells' thresholds ( $- 0.5$ , $1$ , $4 V$ ), and the dashed vertical line is the read voltage $2.5 V$ sitting in the gap. Any cell whose threshold lies to the left of the dashed line conducts. Use it to check each verdict below.

Figure — Floating gate transistor operation

Worked example Will the cell conduct?

Erased threshold $V_{T}^{er} = 1 V$ , programmed threshold $V_{T}^{pr} = 4 V$ . We read with $V_{r e a d} = 2.5 V$ . Decide the read result for three cells: (a) erased, (b) programmed, and (c) a broken over-erased cell with $V_{T} = - 0.5 V$ .

Forecast: Which of the three conducts? Look at the figure's number line first and guess.

Step 1 — State the conduction rule. A cell conducts when the applied gate voltage exceeds its threshold: conduct if $V_{r e a d} > V_{T}$ . Why this step? This is the definition of threshold — below it the channel is OFF, above it ON. We need one crisp rule before testing any cell.

Step 2 — Erased cell (a). $V_{r e a d} = 2.5 > V_{T}^{er} = 1$ → conducts → sense amp reads 1. (Teal zone in figure.) Why this step? Apply the Step-1 rule to the erased threshold specifically: $2.5 > 1$ is true, so the channel is ON and current flows — the sense amp interprets "current present" as a stored 1.

Step 3 — Programmed cell (b). $V_{r e a d} = 2.5 < V_{T}^{pr} = 4$ → stays off → reads 0. (Orange zone.) Why this step? Same rule, programmed threshold: $2.5 > 4$ is false, so no current — "no current" is read as a stored 0. Because $V_{r e a d}$ was placed in the gap, one voltage cleanly splits the two states (see the dashed line in the figure sitting between the ticks).

Step 4 — Over-erased cell (c). $V_{r e a d} = 2.5 > - 0.5$ → conducts — but so would $0 V$ , since $0 > - 0.5$ . Why this step? We push the rule into the degenerate low corner. This cell conducts even with the gate grounded, so it is stuck-ON; it leaks current when unselected, which is why the over-erase of Case B (Ex 2) is a real defect.

Verify: $2.5 > 1$ ✓, $2.5 < 4$ ✓, $2.5 > - 0.5$ ✓ and $0 > - 0.5$ ✓. The read voltage is far below any tunneling field, so $Q_{F G}$ is untouched — non-destructive. See NAND vs NOR Flash architecture for how this decision is wired.

Example 5 — Case E: multi-level packing

The figure below stacks the four MLC charge levels as four horizontal lines (bottom = erased "11", top = most electrons "00"), with the three equal $1 V$ gaps between them labelled — each gap needs about $6250$ electrons. It is the picture of "slicing the charge axis into bands."

Worked example How many electrons per MLC level?

We want an MLC cell (Multi-Level, 2 bits = 4 threshold levels). We spread them across a usable window of $Δ V_{T}$ from $0 V$ up to $3 V$ , with $C_{C G} = 1 fF$ . What charge separates adjacent levels, and how many electrons is that?

Forecast: 4 levels across a $3 V$ window — how many gaps between them, and does each gap need a few dozen or a few thousand electrons?

Step 1 — Count the gaps. 4 levels → 3 gaps between them. Level spacing: $δ (Δ V_{T}) = \frac{3 V}{3} = 1 V per gap$ Why this step? $n$ levels have $n - 1$ intervals — a classic off-by-one to avoid. The evenly-spaced levels are the four bands in the figure.

Step 2 — Charge per gap. Rearrange the engine $Δ V_{T} = - Q / C_{C G}$ to solve for charge magnitude, $∣Δ Q ∣ = C_{C G} ∣Δ V_{T} ∣$ : $∣Δ Q ∣ = 1 \times 1 0^{- 15} \times 1 = 1 \times 1 0^{- 15} C$ Why this step? We know the voltage spacing we want ( $1 V$ ) and must find the charge that produces it — so we run the engine backwards, multiplying instead of dividing. That converts a design target in volts into a physical target in coulombs.

Step 3 — Electrons per gap. $N = \frac{∣Δ Q ∣}{q} = \frac{1 \times 1 0 ^{- 15}}{1.6 \times 1 0 ^{- 19}} = 6250 electrons$ Why this step? Charge in coulombs is abstract; the fab actually controls how many electrons it injects, so we divide by the single-electron charge $q$ to translate coulombs into a countable number. This granularity number is what tells the designer how tightly they must control injection: for QLC (16 levels) the window is sliced 15 ways, so each gap is tiny — that is why QLC is fragile.

Verify: $3/3 = 1$ ✓; $1 \times 1 0^{- 15} /1.6 \times 1 0^{- 19} = 6250$ ✓. Sanity: fewer, wider levels (SLC) need thousands of electrons of margin; more levels shrink that margin — matches the endurance tradeoff.

Example 6 — Case F: design sweep & limiting behaviour

Worked example Doubling the coupling capacitance

We keep the same trapped charge $Q_{F G} = - 1.6 \times 1 0^{- 16} C$ (the 1000-electron program from Ex 1) but a redesign doubles $C_{C G}$ from $1 fF$ to $2 fF$ . What is the new $Δ V_{T}$ , and what happens in the two limits $C_{C G} \to \infty$ and $C_{C G} \to 0$ ?

Forecast: Same charge, bigger capacitor. Does the sensing swing grow or shrink?

Step 1 — Recompute with doubled $C_{C G}$ . $Δ V_{T} = - \frac{- 1.6 \times 1 0 ^{- 16}}{2 \times 1 0 ^{- 15}} = + 0.08 V$ Why this step? $Δ V_{T} \propto 1/ C_{C G}$ : double the capacitor, halve the shift. The same 1000 electrons now buy only $80 mV$ instead of $160 mV$ .

Step 2 — Limit $C_{C G} \to \infty$ . $Δ V_{T} = - Q_{F G} / C_{C G} \to 0$ . Why this step? An enormous coupling capacitor "dilutes" any fixed charge into a vanishing voltage — you lose all sensing margin. Limiting cases catch bad designs.

Step 3 — Limit $C_{C G} \to 0$ . $Δ V_{T} \to \infty$ (blows up). Why this step? A tiny coupling capacitor makes each electron enormously loud — great sensing margin, but the control gate can barely steer the floating gate (poor coupling ratio $α_{G}$ ), so you can't program it cleanly. This is the genuine design tension: sensing margin vs controllability.

Verify: $- (- 1.6 \times 1 0^{- 16}) / (2 \times 1 0^{- 15}) = 0.08$ ✓, exactly half of Example 1's $0.16 V$ ✓. Inverse-proportionality confirmed.

Example 7 — Case G: leakage over time (retention, real-world)

The figure below plots $Δ V_{T}$ (vertical axis, volts) against storage time in years (horizontal axis). The teal curve is the exponential decay starting at $0.16 V$ ; the dashed orange line is the $0.10 V$ read-margin floor; the plum dot marks $t = 10$ years where the curve has fallen to $0.097 V$ — just below the floor. It is the visual of "the bit fades."

Worked example Ten years of slow leak

A programmed cell starts with $Δ V_{T} = 0.16 V$ (the 1000-electron state of Ex 1). Over storage, electrons slowly leak through the oxide so the charge decays as $Q (t) = Q_{0} e^{- t / τ}$ , where $Q_{0} \equiv Q_{F G} (t = 0) = - 1.6 \times 1 0^{- 16} C$ is the initial trapped charge right after programming, and $τ = 20$ years is the time constant (the time to fall to a fraction $1/ e \approx 0.37$ of the start). What is $Δ V_{T}$ after $t = 10$ years? If the read margin needs $Δ V_{T} > 0.10 V$ , does the data survive?

Forecast: After half a time-constant, has more or less than half the shift decayed? (Careful — exponentials aren't linear.)

Step 1 — Why an exponential and not a straight line? Leakage current through the oxide is roughly proportional to the charge still there (more charge → more field across the oxide → more electrons leak per second). "Rate of loss proportional to amount left" is the defining fingerprint of exponential decay — mathematically $\frac{d Q}{d t} = - Q / τ$ , whose solution is exactly $Q (t) = Q_{0} e^{- t / τ}$ . That is why we model retention with $e^{- t / τ}$ and not a linear drain: a linear drain would need a constant leak current, but the field (hence the leak) shrinks as charge leaves.

Step 2 — Since $Δ V_{T} \propto Q$ , the shift decays the same way. $Δ V_{T} (t) = Δ V_{T, 0} e^{- t / τ} = 0.16 \times e^{- 10/20}$ Why this step? The engine $Δ V_{T} = - Q / C_{C G}$ is linear in $Q$ : dividing by the fixed $C_{C G}$ can't change the time-shape, so multiplying $Q$ by $e^{- t / τ}$ multiplies $Δ V_{T}$ by the identical factor. Here $Δ V_{T, 0} = - Q_{0} / C_{C G} = 0.16 V$ is the start value from Ex 1. No need to re-count electrons.

Step 3 — Evaluate the exponent. With $t = 10$ and $τ = 20$ , the exponent is $- 10/20 = - 0.5$ , and $e^{- 0.5} \approx 0.6065$ , so $Δ V_{T} (10) = 0.16 \times 0.6065 \approx 0.0970 V$ Why this step? Plugging in the numbers turns the model into a concrete voltage we can compare against the margin.

Step 4 — Decision. $0.097 < 0.10$ → the margin is lost: after 10 years this cell can no longer be reliably read as programmed. Why this step? Reading only works while the shift stays above the sense-amp floor; once $Δ V_{T}$ drops under $0.10 V$ the programmed cell can be mistaken for erased. Real Flash refreshes / re-writes blocks to fight exactly this. See Charge trap flash and 3D NAND for oxides built to leak slower.

Verify: $0.16 \times e^{- 0.5} = 0.0970$ ✓. Sanity: after one full $τ = 20$ yr it would be $0.16/ e \approx 0.0589 V$ , clearly below margin — consistent with "fails somewhere before 20 years." Forecast: at half a $τ$ , decay factor is $0.61$ , so less than half the shift is gone — exponentials are slow at first.

Example 8 — Case H: exam twist (coupling ratio + intrinsic threshold)

This example is the only place we need $C_{F G}$ — the floating-gate-to-channel capacitance defined at the top. It builds the coupling ratio $α_{G}$ , which we now define.

Worked example Bring in the coupling ratio

The parent note's full formula for the control-gate voltage that switches the cell is $V_{T, obs} = \frac{V _{T 0}}{α _{G}} - \frac{Q _{F G}}{C _{C G}}, α_{G} = \frac{C _{C G}}{C _{C G} + C _{F G}}$ with $V_{T 0} = 0.5 V$ , $C_{C G} = 1 fF$ , $C_{F G} = 1 fF$ , and $Q_{F G} = - 1.6 \times 1 0^{- 16} C$ (programmed). Find $V_{T, obs}$ .

Forecast: Two effects stack — the intrinsic threshold scaled up by $1/ α_{G}$ , plus the charge shift. Will $V_{T, obs}$ be bigger than the naive $0.5 + 0.16 = 0.66 V$ ?

Step 1 — Compute the coupling ratio $α_{G}$ . $α_{G} = \frac{C _{C G}}{C _{C G} + C _{F G}} = \frac{1 \times 1 0 ^{- 15}}{1 \times 1 0 ^{- 15} + 1 \times 1 0 ^{- 15}} = 0.5$ Why this step? The floating gate is squeezed between two capacitors — $C_{C G}$ above (to the control gate) and $C_{F G}$ below (to the channel). Voltage divides across a capacitive divider in proportion to capacitance, so only the fraction $C_{C G} / (C_{C G} + C_{F G})$ of any control-gate swing shows up on the floating gate. With equal capacitors, only half couples through — this is exactly why we need $C_{F G}$ .

Step 2 — The intrinsic term: how $α_{G}$ scales the applied voltage. The channel switches on when the floating-gate voltage reaches $V_{T 0}$ . But we can only push $α_{G}$ of what we apply. So to make the floating gate reach $V_{T 0}$ , we must apply $V_{T 0} / α_{G}$ at the control gate: $\frac{V _{T 0}}{α _{G}} = \frac{0.5}{0.5} = 1.0 V$ Why this step? This is the concrete meaning of " $α_{G}$ modifies the applied gate voltage": a coupling of $0.5$ doubles the control-gate voltage you must supply. Even an empty gate already needs $1.0 V$ to switch, not $0.5 V$ .

Step 3 — Add the charge shift (the engine from Ex 1). $V_{T, obs} = \frac{V _{T 0}}{α _{G}} - \frac{Q _{F G}}{C _{C G}} = 1.0 - \frac{- 1.6 \times 1 0 ^{- 16}}{1 \times 1 0 ^{- 15}} = 1.0 + 0.16 = 1.16 V$ Why this step? The observed threshold combines both effects: the coupling penalty ( $1.0 V$ ) that even an erased cell pays, plus the trapped-charge shift ( $+ 0.16 V$ ) from the stored electrons. The charge term $- Q_{F G} / C_{C G}$ is exactly the engine we used all page — untouched by $α_{G}$ , which only scales the intrinsic part.

Step 4 — Why the naive answer is wrong. The tempting shortcut $0.5 + 0.16 = 0.66 V$ forgets that imperfect coupling inflates the intrinsic threshold from $0.5 V$ to $1.0 V$ before any charge is added. The real answer, $1.16 V$ , is $0.5 V$ higher — a big miss on an exam. Practical implication: poor coupling ( $α_{G}$ small) forces higher program/read voltages, which stresses the oxide and shortens cell life — the same tension flagged in Example 6.

Verify: $α_{G} = 0.5$ ✓; $0.5/0.5 = 1.0$ ✓; $1.0 + 0.16 = 1.16$ ✓. Sanity: the pure-shift piece ( $0.16 V$ ) matches Example 1 exactly, confirming the charge term is unchanged by adding the coupling term.

Recall

Recall Which case had

$Δ V_{T}$ go below baseline, and why? Case B (Ex 2), over-erase ::: net positive trapped charge makes $Δ V_{T} = - Q / C_{C G} < 0$ ; the cell turns on too easily and can be stuck-ON.

Recall Doubling

$C_{C G}$ does what to the sensing swing? Halves it ::: because $Δ V_{T} \propto 1/ C_{C G}$ (Ex 6).

Recall Why does the threshold decay

exponentially over years, not linearly? Leak rate is proportional to the charge remaining ::: "rate ∝ amount" ( $d Q / d t = - Q / τ$ ) is the signature of exponential decay (Ex 7).

Recall In the full formula, why is the intrinsic term

$V_{T 0} / α_{G}$ larger than $V_{T 0}$ ? Only a fraction $α_{G} < 1$ of the control-gate voltage couples to the floating gate ::: so you must over-apply by $1/ α_{G}$ to reach the intrinsic threshold (Ex 8).