Visual walkthrough — Floating gate transistor operation

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Step 1 — What "turn-on" even means (the plain MOSFET)

WHAT. A MOSFET is a switch. A metal-ish gate sits over a silicon channel, separated by a thin insulator (oxide). When the gate voltage is small, no current flows between the two terminals (source and drain). Push the gate voltage high enough and a conducting bridge of electrons forms under the oxide — the switch turns on.

WHY. We need one crisp number that says "the switch flips here." That number is the threshold voltage, written $V_T$. Read it as: the gate voltage at which the channel first conducts.

PICTURE. Below: raise the gate voltage (green needle sweeping right). Left of the red line = off (no channel). Right of it = on (channel filled). The red line is $V_T$.

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Step 2 — Bury a second gate that nothing touches

WHAT. Slide an extra slab of conductor inside the oxide, between the gate and the channel. Wrap it completely in insulator so no wire reaches it. This is the floating gate (FG). The original driven gate is now the control gate (CG).

WHY. A conductor with no wire is a charge trap. Put electrons on it and they cannot flow away — there is no path. That trapped charge will be our stored bit. But now the FG's voltage is not something we set directly; it is whatever physics forces it to be. Steps 3–5 compute it.

PICTURE. The stack, bottom to top: channel, thin tunnel oxide, floating gate (lavender, isolated), thicker control oxide, control gate (the only terminal with a wire).

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Step 3 — Two capacitors, sharing one middle plate

WHAT. Any two conductors separated by insulator form a capacitor — a device that stores a voltage-proportional charge, $Q=CV$, where $C$ (the capacitance) measures how much charge one volt buys. The floating gate is a conductor sandwiched between two others, so it is the shared middle plate of two capacitors:

• $C_{CG}$ — between control gate and floating gate.
• $C_{FG}$ — between floating gate and the channel below.

WHY. We invoke capacitance because it is the only tool that links a conductor's charge to its voltage without a wire. The FG has no wire, so charge–voltage coupling is the only way it feels the outside world. That is exactly the question a capacitor answers.

PICTURE. Two capacitors stacked in series, floating gate as the common plate in the middle. Top plate = control gate at voltage $V_{CG}$; bottom plate = channel, which we anchor at $0$ volts as our reference.

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Step 4 — Charge on the middle plate must add up (conservation)

WHAT. Let $V_{FG}$ be the floating gate's (unknown) voltage and $Q_{FG}$ the charge we trapped on it. The charge on the FG plate is the sum contributed through each capacitor it belongs to:

$Q_{FG}=\underset{\text{coupling to CG}}{\underbrace{C_{CG}}}\underset{\text{volts across top cap}}{\underbrace{(V_{FG}-V_{CG})}}+\underset{\text{coupling to channel}}{\underbrace{C_{FG}}}\underset{\text{volts across bottom cap}}{\underbrace{(V_{FG}-0)}}$

Term by term: the first product is the charge the FG holds facing the control gate (voltage difference $V_{FG}-V_{CG}$ times its capacitance); the second is the charge it holds facing the channel (difference $V_{FG}-V_{ch}$, and we chose $V_{ch}=0$). Their sum is the total trapped charge $Q_{FG}$.

WHY. Charge cannot appear or vanish on an isolated plate — conservation. So whatever charge we injected must equal what the two capacitors account for. One equation, one unknown ($V_{FG}$). Solve it.

PICTURE. Arrows show charge flowing "into" the middle plate from each capacitor; the tally must equal the trapped lump $Q_{FG}$ shown as a cluster of electrons.

Now solve for the middle-plate voltage. Group the $V_{FG}$ terms:

$Q_{FG}=(C_{CG}+C_{FG})V_{FG}-C_{CG}{V}_{CG}$

$\boxed{V_{FG}=\underset{\text{coupling ratio }{\alpha }_G}{\underbrace{\frac{C_{CG}}{C_{CG}+C_{FG}}}}{V}_{CG}+\frac{Q_{FG}}{C_{CG}+C_{FG}}}$

Read it: the FG voltage is a fraction ${\alpha }_G$ of the control voltage (a capacitive divider — the top cap "grabs" only its share) plus a bump from the trapped charge. No charge ($Q_{FG}=0$) → the FG just follows a scaled copy of the control gate.

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Step 5 — The channel obeys $V_{FG}$, not $V_{CG}$ — so charge moves the threshold

WHAT. The channel only "sees" the floating gate right above it. So the switch turns on when $V_{FG}$ hits the plain silicon threshold, call it $V_{T0}$ (the value a normal MOSFET would have). Set $V_{FG}=V_{T0}$ in the boxed result and solve for the control voltage $V_{CG}$ we must apply from outside:

$V_{T0}={\alpha }_G{V}_{CG}+\frac{Q_{FG}}{C_{CG}+C_{FG}}$

$V_{CG}=\frac{V_{T0}}{{\alpha }_G}-\frac{Q_{FG}}{{\alpha }_G(C_{CG}+C_{FG})}$

The second denominator simplifies: ${\alpha }_G(C_{CG}+C_{FG})=C_{CG}$. So the control voltage needed — the observed threshold — is:

$V_{T,\text{obs}}=\underset{\text{fixed baseline}}{\underbrace{\frac{V_{T0}}{{\alpha }_G}}}-\underset{\text{moves with charge}}{\underbrace{\frac{Q_{FG}}{C_{CG}}}}$

WHY. The first term is a constant of the device. The second term is the only part that changes when we trap charge — and it is our memory. Subtract the two states:

$\boxed{\Delta V_T=-\frac{Q_{FG}}{C_{CG}}}$

PICTURE. The red $V_T$ line from Step 1, now shown sliding: trap negative electrons ($Q_{FG}<0$) and the line moves right (higher $V_T$, harder to turn on = programmed, a stored 0); remove them and it slides back left (erased, a 1).

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Step 6 — Edge cases: every sign, and the degenerate limits

We must not leave a scenario unshown.

• $Q_{FG}=0$ (fresh cell): $\Delta V_T=0$. Observed threshold is the baseline $V_{T0}/{\alpha }_G$. This is the erased-ish middle state before any writing.
• $Q_{FG}<0$ (electrons trapped): $\Delta V_T=-(\text{negative})/C_{CG}=+$. Threshold rises → programmed → 0.
• $Q_{FG}>0$ (net positive, e.g. holes / over-erased): $\Delta V_T<0$. Threshold drops below baseline. Over-erase this far and the cell can conduct even at $V_{CG}=0$ — a real failure mode called depletion/over-erase.
• $C_{CG}$ small (weak coupling): $|\Delta V_T|$ is large for the same charge — a big, easy-to-sense swing, but ${\alpha }_G$ suffers so you need a bigger $V_{CG}$ to operate.
• $C_{CG}$ large: $|\Delta V_T|$ shrinks — the same electrons make a smaller swing (harder to sense). This is the design tension the parent note flagged.

PICTURE. One number line of $V_T$ with three cells marked: over-erased (left of baseline), erased/fresh (baseline), programmed (right), plus the read voltage sitting between erased and programmed.

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Step 7 — Reading and the multi-level payoff (worked numbers)

WHAT. Place a read voltage strictly between the two thresholds and watch for current.

$V_T(\text{erased})<V_{read}<V_T(\text{programmed})$

Worked read — erased $V_T=1\text{V}$, programmed $V_T=4\text{V}$, read at $2.5\text{V}$:

• Erased: $2.5>1$ → conducts → 1.
• Programmed: $2.5<4$ → off → 0.

Worked shift — $C_{CG}=1\text{fF}=1\times 10^{-15}\text{F}$, inject $N=1000$ electrons ($q=1.6\times 10^{-19}\text{C}$):

$Q_{FG}=-Nq=-1.6\times 10^{-16}\text{C},\Delta V_T=-\frac{Q_{FG}}{C_{CG}}=+0.16\text{V}$

WHY. Because $\Delta V_T$ is continuous in charge, we can carve the axis into 4, 8, or 16 windows → 2, 3, 4 bits per cell (see Multi-level cell (MLC TLC QLC)). More windows = tighter margins = less endurance.

PICTURE. The $V_T$ axis sliced into 4 shaded bands (an MLC cell), with the read reference lines that separate them.

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The one-picture summary

One figure, whole derivation: two series capacitors set $V_{FG}$; conservation gives $V_{FG}={\alpha }_G{V}_{CG}+Q_{FG}/(C_{CG}+C_{FG})$; the channel triggers when $V_{FG}=V_{T0}$; the leftover charge term becomes $\Delta V_T=-Q_{FG}/C_{CG}$, sliding the red threshold line and encoding the bit.

Recall Feynman retelling — say it in plain words

Imagine a light switch you flip by turning a dial to a certain mark. Now sneak a tiny magnet behind the dial that makes it stiffer, so you have to turn further to flip the switch. The magnet is trapped charge; "how much further" is $\Delta V_T$. Because the dial (control gate) and the magnet's pocket (floating gate) are two plates facing each other, "how much further per unit charge" is set by their capacitance $C_{CG}$ — small pocket, big effect: $\Delta V_T=-Q/C_{CG}$. Electrons make it stiffer (a 0); yank them out and it flips easily again (a 1). Reading is just wiggling the dial gently between the two marks and checking if the light comes on — too gentle to move the magnet, so it never erases what it reads.

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See also: Fowler-Nordheim tunneling and Channel hot-electron injection (how charge crosses the oxide), NAND vs NOR Flash architecture, Charge trap flash and 3D NAND, EEPROM and EPROM.