Floating gate transistor operation: Question bank — Hardware deep dive

Every symbol and term this page uses, defined first

Before any trap, here is the full vocabulary — nothing below is used before it appears here.

Definition The quantities

Control gate — the terminal you actually drive with a wire. $V_{C G}$ = the voltage you apply to it. This is the only voltage you control directly.
Floating gate (FG) — the buried, wire-less conducting gate wrapped in oxide. Its own voltage $V_{F G}$ cannot be set directly; it floats to whatever the surrounding capacitors and trapped charge force it to be.
$Q_{F G}$ = the trapped charge on the floating gate. Electrons make it negative.
$V_{T}$ = the threshold voltage: the control-gate voltage $V_{C G}$ at which the channel finally turns on.
$V_{T 0}$ = the intrinsic threshold — the turn-on threshold of the underlying MOSFET before we account for coupling and trapped charge (i.e. the value the plain MOSFET would show). $V_{r e a d}$ = the voltage placed between the erased and programmed thresholds for sensing.

Where the core law comes from (visual + one-line algebra)

The floating gate is a node with charge $Q_{F G}$ sitting between two series capacitors (figure below). Treating it as a capacitive divider with an added charge term (derived in full in Floating gate transistor operation) gives the floating-gate voltage $V_{F G} = α_{G} V_{C G} + Q_{F G} / C_{t o t}$ . Setting $V_{F G} = V_{T 0}$ (the point the channel turns on) and solving for the control voltage we must apply yields the observed threshold, whose shift relative to no charge is:

$Δ V_{T} = - \frac{Q _{F G}}{C _{C G}}$

Figure — Floating gate transistor operation

Reading and the two mechanisms side by side:

True or false — justify

The floating gate is wired to the control gate through a thin metal strap

False. The floating gate connects to nothing; it is wrapped in oxide on all sides. That total isolation is why charge stays put and the cell is non-volatile.

Adding electrons to the floating gate makes the transistor easier to turn on

False. Trapped electrons are negative, so they oppose the control gate's field; you need a larger control-gate voltage

V_{C G}

to invert the channel, so

V_{T}

rises. The electrons are on the gate, not carrying current in the channel.

A floating gate cell keeps its bit even with the power supply removed

True. There is no leakage path off the isolated gate, so

Q_{F G}

is retained for years — this is the definition of non-volatile storage.

The "programmed" state has a lower threshold than the "erased" state

False. Programmed means electrons stored → high

V_{T}

; erased means charge removed → low

V_{T}

. The read voltage sits between them.

A single read operation can slowly erase the stored bit

False for a single read.

V_{r e a d}

is far below the tunneling/injection field, so it is non-destructive. Only repeated reads cause the separate "read disturb" effect over time.

Because

Δ V_{T}

depends continuously on

Q_{F G}

, one cell can encode more than one bit

True. Splitting the charge axis into 4/8/16 distinguishable levels gives 2/3/4 bits — MLC/TLC/QLC. See Multi-level cell (MLC TLC QLC).

Fowler–Nordheim tunneling and hot-electron injection are the same physical process

False. FN is quantum tunneling through a field-thinned barrier at low current; CHE is electrons gaining kinetic energy and jumping over the barrier at higher current. Different physics, different uses (see the side-by-side figure above).

Spot the error

"In floating-gate NAND, FN tunneling does both the program and the erase."

Error: in FG NAND, program = channel hot-electron injection, erase = FN tunneling. FN's whole-gate low-current action suits block erase; CHE's targeted injection suits selective programming.

"Since electrons are current carriers, storing them on the gate increases channel current."

Error: these electrons are stuck on the isolated gate, not free in the channel. Their charge repels the control field and reduces the channel's tendency to conduct, raising

V_{T}

"Doubling

C_{C G}

while keeping

Q_{F G}

fixed doubles the readable threshold swing."

Error:

Δ V_{T} = - Q_{F G} / C_{C G}

is inversely proportional to

C_{C G}

, so doubling it halves the swing. Bigger coupling dilutes the same charge into a smaller voltage.

"The floating gate is called 'floating' because it physically moves inside the oxide."

Error: "floating" is an electrical term — its potential

V_{F G}

floats to whatever the capacitor network and

Q_{F G}

force, because no wire pins it down. Nothing moves mechanically.

"To read the cell you apply the same high voltage used to program it."

Error: read uses a small

V_{r e a d}

placed between the two thresholds so it can sense conduction without disturbing

Q_{F G}

. Programming voltages are far higher and would tunnel/inject charge.

"NOR and NAND floating-gate cells differ because NOR has no floating gate."

Error: both have floating gates. They differ in array wiring and, historically, program mechanism emphasis — see NAND vs NOR Flash architecture — not in the cell's basic structure.

"Only

C_{C G}

matters; the source, drain, and substrate have no capacitance to the floating gate."

Error: the floating gate couples to all of them (

C_{S}

C_{D}

C_{B}

), and their sum

C_{F G}

enters the total

C_{t o t}

that sets the coupling ratio

α_{G}

and the floating-gate potential. Ignoring them is only a first-pass simplification.

Why questions

Why must a floating gate transistor use tunneling or hot-electron injection instead of just a wire to load charge?

Because the gate is fully isolated — there is no conductive path. Charge can only cross the oxide via quantum tunneling (Fowler-Nordheim tunneling) or by jumping the barrier with enough energy (Channel hot-electron injection).

Why does adding negative charge give a positive

Δ V_{T}

Δ V_{T} = - Q_{F G} / C_{C G}

, a negative

Q_{F G}

times the minus sign yields a positive shift. Physically the electrons oppose the control gate, demanding a higher

V_{C G}

to turn on.

Why is the tunnel oxide thin (~8–10 nm) but the inter-poly oxide thicker?

The thin tunnel oxide lets electrons cross deliberately during program/erase; the thicker top oxide blocks charge from escaping upward during storage, keeping retention high.

Why does a mere ~1000 electrons produce a usefully large threshold shift?

With a tiny

C_{C G} \sim 1 fF

Δ V_{T} = - Q / C_{C G}

turns a small charge into ~160 mV — measurable by the sense amp. Small capacitance is what makes so few electrons "loud."

Why do designers face tension between coupling ratio

α_{G}

and sensing margin?

A large

C_{C G}

raises

α_{G} = C_{C G} / C_{t o t}

, giving the control gate strong grip on the floating gate — but the same large

C_{C G}

shrinks

Δ V_{T} = - Q_{F G} / C_{C G}

for fixed charge (worse margin). You cannot maximize both from the one capacitor.

Why does repeated reading eventually disturb the bit even though one read is safe?

Each read still drops a small field across the tunnel oxide. One read moves essentially no charge, but summed over thousands of reads that weak field can leak a few electrons across (read disturb), slowly drifting

V_{T}

Why does going from MLC to QLC reduce endurance and speed?

More levels squeeze the same

V_{T}

window into narrower slices, leaving less error margin. Distinguishing them needs more careful, slower programming and tolerates fewer wear-induced shifts.

Edge cases

If a freshly-erased cell has exactly

Q_{F G} = 0

, what is its threshold?

It equals the intrinsic threshold scaled by coupling,

V_{T 0} / α_{G}

, with

Δ V_{T} = 0

. Zero trapped charge means no shift — this is the reference "erased" state (

V_{T 0}

being the plain-MOSFET turn-on level).

Read voltage is set below both thresholds (too small). What does every cell report?

Every cell stays off → all read as programmed/0. The read window is broken because

V_{r e a d}

no longer separates erased from programmed states.

Read voltage is set above both thresholds (too large). What does every cell report?

Every cell conducts → all read as erased/1. Again the bit is unresolvable;

V_{r e a d}

must lie strictly between the two thresholds.

Over years, a few electrons slowly leak off a programmed cell — what happens to the bit?

∣ Q_{F G} ∣

shrinks, so

V_{T}

drifts down toward the erased level. If it crosses

V_{r e a d}

, a stored 0 is misread as 1 — this is retention-loss data corruption.

A cell is programmed with far too many electrons so its

V_{T}

overshoots the read window's top. Is that fine?

For a single-level cell it still reads 0 (stays off), so it's tolerable. But in MLC/TLC it can invade a neighboring level's band and corrupt the multi-bit value.

What if the tunnel oxide is made much thicker to improve retention — any cost?

Retention improves (less leakage), but the same program/erase voltage now produces a weaker field, so tunneling/injection is harder — slower, higher-voltage writes. Retention and writability trade off.

Charge-trap flash stores charge in an insulator instead of a conductive floating gate — does

Δ V_{T} = - Q / C_{C G}

still hold?

The same electrostatic principle applies: trapped negative charge still raises

V_{T}

. The difference is the charge is held in discrete traps, giving better immunity to single-defect leakage — see Charge trap flash and 3D NAND.

Recall One-line summary to keep

Every trap above reduces to one law and one fact: $Δ V_{T} = - Q_{F G} / C_{C G}$ (negative charge → higher threshold) on a gate whose potential $V_{F G}$ floats and connects to nothing.