Floating gate transistor operation: Exercises — Hardware deep dive

Definition Symbols used on this page (define once, reuse everywhere)

$V_{T}$ — the threshold voltage: the control-gate voltage at which the channel just turns on and current starts to flow.
$Δ V_{T}$ — the threshold shift: how much $V_{T}$ moves when charge is added to or removed from the floating gate. It is the change, not the value itself.
$C_{C G}$ — capacitance between the control gate and the floating gate.
$C_{F G}$ — capacitance between the floating gate and the channel/substrate (the other capacitor in the stack). It appears whenever we compute the coupling ratio.
$V_{T 0}$ — the intrinsic threshold: the value the floating gate itself would need to reach to turn on the channel (a fixed property of the underlying MOSFET).
$V_{T, obs}$ — the observed threshold at the control gate: what you actually measure when driving $V_{C G}$ . When there is zero trapped charge we call this baseline $V_{T, obs, 0}$ .
$α_{G}$ — the gate coupling ratio $C_{C G} / (C_{C G} + C_{F G})$ : the fraction of the control-gate voltage that actually reaches the floating gate.

Before we start, here is the picture every numeric problem leans on — the two capacitors that sandwich the floating gate, so you always know which capacitance a symbol refers to. The upper capacitor is $C_{C G}$ ; the lower one, between the floating gate and the channel, is $C_{F G}$ .

Figure — Floating gate transistor operation

Reference constants used throughout:

Electron charge magnitude $q = 1.6 \times 1 0^{- 19} C$ .
$1 fF = 1 \times 1 0^{- 15} F$ , $1 aF = 1 \times 1 0^{- 18} F$ .
$1 mV = 1 0^{- 3} V$ .

Level 1 — Recognition

Problem 1.1

A floating gate transistor differs from an ordinary MOSFET by having one extra structural element. Name it, and state the one property that makes it able to store data with the power off.

Recall Solution

What: The extra element is the floating gate — a conducting (poly-silicon) gate buried in the oxide between the control gate and the channel. Why non-volatile: it is completely wrapped in insulating oxide, so it connects to nothing. Any charge placed on it has nowhere to leak to, so the charge — and therefore the stored bit — survives with no power applied.

Problem 1.2

In the formula $Δ V_{T} = - Q_{F G} / C_{C G}$ , an FG cell has electrons stored on it. State the sign of $Q_{F G}$ and the sign of $Δ V_{T}$ , and say whether this is the programmed or erased state.

Recall Solution

Electrons carry negative charge, so $Q_{F G} < 0$ . Then $Δ V_{T} = - Q_{F G} / C_{C G} = - (negative) / (positive) > 0$ , so $Δ V_{T} > 0$ . A higher threshold means the transistor is harder to turn on — this is the programmed state (stores a logical 0).

Level 2 — Application

Problem 2.1

A cell has $C_{C G} = 2 fF$ . We inject $N = 2500$ electrons onto the floating gate. Find $Δ V_{T}$ (magnitude and sign).

Recall Solution

Step 1 — find the charge. Each electron adds $- q$ . So $Q_{F G} = - N q = - 2500 \times 1.6 \times 1 0^{- 19} = - 4.0 \times 1 0^{- 16} C .$ Why negative: electrons carry negative charge. Step 2 — apply the master formula. $Δ V_{T} = - \frac{Q _{F G}}{C _{C G}} = - \frac{- 4.0 \times 1 0 ^{- 16}}{2 \times 1 0 ^{- 15}} = + 0.20 V .$ Why the answer comes out positive: the formula already carries a leading minus, and the charge we plug in is itself negative (electrons). A minus times a negative number is positive — the two minus signs cancel, leaving $Δ V_{T} > 0$ . Physically, negative charge on the gate opposes the control-gate field, so the threshold must rise; the algebra's double-negative is just that physical fact written down. Answer: $Δ V_{T} = + 0.20 V$ (threshold rises by 200 mV). This is a programming shift.

Problem 2.2

Erased $V_{T} = 1.2 V$ , programmed $V_{T} = 4.2 V$ . We read with $V_{r e a d} = 3.0 V$ . For each state, does current flow, and what bit is sensed?

Recall Solution

A cell conducts when the applied gate voltage exceeds its threshold.

Erased cell ( $V_{T} = 1.2 V$ ): $3.0 > 1.2$ → channel inverts → current flows → sensed as 1.
Programmed cell ( $V_{T} = 4.2 V$ ): $3.0 < 4.2$ → channel stays off → no current → sensed as 0. The read voltage sits between the two thresholds, which is exactly the condition $V_{T} (erased) < V_{r e a d} < V_{T} (programmed) .$

Level 3 — Analysis

Problem 3.1

A cell has $C_{C G} = 1.0 fF$ and $C_{F G} = 1.5 fF$ (recall from the symbol list: $C_{F G}$ is the capacitance between the floating gate and the channel — the lower capacitor in the stack figure). Compute the gate coupling ratio $α_{G} = C_{C G} / (C_{C G} + C_{F G})$ . Then, with intrinsic threshold $V_{T 0} = 0.5 V$ and zero trapped charge, find the observed control-gate threshold $V_{T, obs} = V_{T 0} / α_{G}$ .

Recall Solution

Step 1 — coupling ratio. This fraction says how much of the control voltage actually reaches the floating gate through capacitive division between the two stacked capacitors $C_{C G}$ (top) and $C_{F G}$ (bottom). $α_{G} = \frac{C _{C G}}{C _{C G} + C _{F G}} = \frac{1.0}{1.0 + 1.5} = \frac{1.0}{2.5} = 0.40.$ Step 2 — observed threshold with no charge. Since only a fraction $α_{G}$ of $V_{C G}$ reaches the FG, we must over-drive the control gate to make $V_{F G}$ hit $V_{T 0}$ : $V_{T, obs} = \frac{V _{T 0}}{α _{G}} = \frac{0.5}{0.40} = 1.25 V .$ Answer: $α_{G} = 0.40$ , $V_{T, obs} = 1.25 V$ .

Problem 3.2

Take the same cell (from 3.1: $C_{C G} = 1.0 fF$ , $α_{G} = 0.40$ , baseline $V_{T, obs, 0} = 1.25 V$ — the observed threshold with zero trapped charge). Now inject $N = 4000$ electrons. Using the full relation $V_{T, obs} = \frac{V _{T 0}}{α _{G}} - \frac{Q _{F G}}{C _{C G}},$ find the new observed threshold.

Recall Solution

Step 1 — trapped charge. $Q_{F G} = - N q = - 4000 \times 1.6 \times 1 0^{- 19} = - 6.4 \times 1 0^{- 16} C .$ Step 2 — the shift term. $- \frac{Q _{F G}}{C _{C G}} = - \frac{- 6.4 \times 1 0 ^{- 16}}{1.0 \times 1 0 ^{- 15}} = + 0.64 V .$ Step 3 — add to the uncharged threshold. $V_{T, obs} = 1.25 + 0.64 = 1.89 V .$ Answer: the programmed threshold is $1.89 V$ , i.e. $0.64 V$ above the erased value.

The figure below draws exactly this result on a voltage axis: the green line is the erased/baseline threshold ( $1.25 V$ ), the red line is the programmed threshold ( $1.89 V$ ) after the $4000$ electrons, the blue arrow is the $Δ V_{T} = 0.64 V$ shift you just computed, and the yellow dashed line shows where a read voltage would sit to distinguish the two states.

Level 4 — Synthesis

Problem 4.1 — MLC window budget

A cell must store 2 bits using 4 distinct $V_{T}$ levels (an MLC cell). The usable threshold window runs from $V_{T} = 1.0 V$ (erased, level 0) to $V_{T} = 5.5 V$ (fully programmed, level 3), and the 4 levels are spaced equally. Find (a) the level spacing $Δ$ , and (b) with $C_{C G} = 1.0 fF$ , how many extra electrons you must add to move from one level to the next.

Recall Solution

Step 1 — level spacing. 4 levels span the window in 3 equal gaps: $Δ = \frac{5.5 - 1.0}{4 - 1} = \frac{4.5}{3} = 1.5 V .$ Why $4 - 1$ : $n$ levels have $n - 1$ gaps between them, like 4 fence posts with 3 gaps. Step 2 — electrons per step. Each step needs a threshold shift of $Δ = 1.5 V$ . From $Δ V_{T} = - Q / C_{C G}$ , the charge required is $∣ Q ∣ = C_{C G} Δ V_{T}$ : $∣ Q ∣ = 1.0 \times 1 0^{- 15} \times 1.5 = 1.5 \times 1 0^{- 15} C .$ Number of electrons: $N = \frac{∣ Q ∣}{q} = \frac{1.5 \times 1 0 ^{- 15}}{1.6 \times 1 0 ^{- 19}} \approx 9375 electrons .$ Answer: $Δ = 1.5 V$ per level; about 9375 electrons per step.

Problem 4.2 — TLC squeeze

Now cram 3 bits (8 levels, TLC) into the same $1.0$ – $5.5 V$ window. Find the new level spacing $Δ^{'}$ and explain, in one line, why endurance and error-margin get worse.

Recall Solution

Step 1 — spacing. 8 levels → 7 gaps: $Δ^{'} = \frac{5.5 - 1.0}{8 - 1} = \frac{4.5}{7} \approx 0.643 V .$ Step 2 — the tradeoff. The window is fixed but now sliced into narrower bins ( $0.64 V$ vs $1.5 V$ ). A given amount of oxide leakage or read-disturb noise now overlaps neighbouring levels far more easily, so the cell tolerates less charge drift → lower endurance and thinner error margin for more capacity. This is the exact MLC/TLC/QLC bargain.

Level 5 — Mastery

Problem 5.1 — Retention / data-loss estimate

A programmed cell starts with $N_{0} = 12000$ electrons on the floating gate ( $C_{C G} = 1.0 fF$ ). Because the tunnel oxide is not perfect, electrons leak so that the count decays exponentially with a retention time constant $τ$ : $N (t) = N_{0} e^{- t / τ}, τ = 10 years .$ The cell is still read correctly as long as its threshold shift stays at least $0.5 V$ above the erased level. How long until the cell fails (its programming shift $Δ V_{T}$ drops to $0.5 V$ )?

Recall Solution

Step 1 — threshold shift as a function of electron count. Start from the master formula with electrons only, i.e. $Q_{F G} = - N q$ (negative charge). Substitute: $Δ V_{T} = - \frac{Q _{F G}}{C _{C G}} = - \frac{( - N q )}{C _{C G}} = + \frac{N q}{C _{C G}} .$ Why the sign flips: the master formula carries a leading minus, and the charge we substitute, $- N q$ , is itself negative. Minus times a negative gives a plus, so the two minus signs cancel and $Δ V_{T}$ comes out positive — exactly what a programmed (electron-loaded) cell should have. The shift is therefore proportional to the electron count $N$ . Step 2 — initial shift. $Δ V_{T, 0} = \frac{N _{0} q}{C _{C G}} = \frac{12000 \times 1.6 \times 1 0 ^{- 19}}{1.0 \times 1 0 ^{- 15}} = 1.92 V .$ Step 3 — failure condition. Failure when $Δ V_{T} (t) = 0.5 V$ . Since $Δ V_{T} \propto N$ , and $N$ decays like $e^{- t / τ}$ : $\frac{Δ V _{T} ( t )}{Δ V _{T, 0}} = e^{- t / τ} = \frac{0.5}{1.92} .$ Step 4 — solve for $t$ . Take the natural log (the tool that "undoes" the exponential — it answers "e to what power gives this ratio?"): $t = - τ ln (\frac{0.5}{1.92}) = - 10 \times ln (0.2604) = - 10 \times (- 1.346) \approx 13.5 years .$ Answer: the cell holds valid data for about 13.5 years before leakage drops the shift below the $0.5 V$ margin.

Problem 5.2 — Design trade with coupling ratio

A designer doubles $C_{C G}$ (better control-gate coupling) while keeping the trapped charge $Q_{F G}$ the same. (a) What happens to the sensing shift $∣Δ V_{T} ∣$ ? (b) If originally $C_{C G} = 1.0 fF$ gave $∣Δ V_{T} ∣ = 0.32 V$ for some fixed charge, what is $∣Δ V_{T} ∣$ after doubling?

Recall Solution

(a) Since $Δ V_{T} = - Q_{F G} / C_{C G}$ is inversely proportional to $C_{C G}$ , doubling $C_{C G}$ halves $∣Δ V_{T} ∣$ . The same trapped charge is "diluted" over a larger capacitance, giving a smaller voltage swing — worse sensing margin even though coupling improved. This is the real design tension between $α_{G}$ and margin. (b) New value: $∣Δ V_{T} ∣_{new} = \frac{0.32}{2} = 0.16 V .$

Recall One-line self-check on the master formula

Why is $Δ V_{T}$ inversely proportional to $C_{C G}$ ? ::: The same trapped charge $Q_{F G}$ produces a voltage $Q_{F G} / C_{C G}$ ; a larger $C_{C G}$ spreads that charge into a smaller voltage, so the observable threshold shift shrinks. Why does a TLC cell wear out sooner than an MLC cell in the same window? ::: TLC slices the fixed $V_{T}$ window into more, narrower level-bins, so smaller charge drift/leakage already pushes a cell into a wrong bin.