Floating gate transistor operation

4.1.9 · Hardware › Memory Technologies

YEH HAI KYA?

Stack, neeche se upar:

1. Channel / substrate (silicon, jisme source & drain hain).
2. Tunnel oxide (patla, ~8–10 nm) — electrons isi se cross karke FG tak pahunchte hain.
3. Floating gate (poly-silicon, isolated) — charge store karne ki jagah.
4. Inter-poly / control oxide (mota) — charge ko upar ki taraf escape karne se rokta hai.
5. Control gate (woh terminal jo aap actually drive karte ho).

STORED CHARGE BIT KO ENCODE KYUN KARTA HAI? (Threshold shift derive karo)

KYUN: Ek ordinary MOSFET mein, channel tab turn on hota hai jab control-gate voltage threshold $V_T$ se zyada ho jaye. Agar hum $V_T$ ko marzi se badal sakein aur woh badla hua rehe, toh hamare paas memory hai.

KAISE — $\Delta V_T$ ko charge conservation se derive karo.

Floating gate ko do series capacitors ki beech wali plate samjho:

• $C_{CG}$ = control gate aur floating gate ke beech capacitance.
• $C_{FG}$ = floating gate aur channel/substrate (aur source/drain) ke beech capacitance.

Floating-gate potential $V_{FG}$, control voltage $V_{CG}$ ki capacitive division se set hoti hai, saath mein jo bhi charge $Q_{FG}$ gate pe baitha hai woh bhi effect karta hai. FG node pe charge ke hisaab se:

$Q_{FG}=C_{CG}(V_{FG}-V_{CG})+C_{FG}(V_{FG}-V_{ch})$

$V_{FG}$ ke liye solve karo ($V_{ch}=0$ reference lo):

$V_{FG}=\underset{\text{coupling ratio }{\alpha }_G}{\underbrace{\frac{C_{CG}}{C_{CG}+C_{FG}}}}{V}_{CG}+\frac{Q_{FG}}{C_{CG}+C_{FG}}$

Yeh step kyun? FG floating hai, isliye iski voltage directly drive nahi hoti — woh jo bhi capacitor network + trapped charge force karta hai, wahi hoti hai. Yeh exactly ek capacitive divider hai jisme extra charge term hai.

Device tab conduct karta hai jab $V_{FG}$ intrinsic threshold $V_{T0}$ tak pahunche. $V_{FG}=V_{T0}$ set karke aur jo control-gate voltage apply karni padegi uske liye solve karo:

$V_{T,\text{observed}}=\frac{V_{T0}}{{\alpha }_G}-\frac{Q_{FG}}{C_{CG}}$

Sign kyun: FG pe electrons control gate ke field ko electrostatically oppose karte hain, isliye channel invert karne ke liye zyada bada $V_{CG}$ chahiye.

ELECTRONS ISOLATED GATE PE AATE/JAATE KAISE HAIN?

Woh wires se flow nahi kar sakte (woh isolated hai!), isliye hum patli tunnel oxide ke across quantum & high-field mechanisms use karte hain:

Bit read karna: ek read voltage $V_{read}$ apply karo jo dono thresholds ke beech ho. Agar cell conduct karta hai → woh erased/low-$V_T$ state hai (1); agar off rehta hai → programmed/high-$V_T$ state hai (0).

$V_T(\text{erased})<V_{read}<V_T(\text{programmed})$

Multi-Level Cells (80/20 payoff idea)

Kyunki $\Delta V_T$, $Q_{FG}$ mein continuous hai, hum ek cell mein ek se zyada $V_T$ level store kar sakte hain. 4 distinct charge levels → 2 bits (MLC); 8 levels → 3 bits (TLC); 16 → 4 bits (QLC). Tradeoff kyun: zyada levels = zyada narrow voltage windows = kam error margin = slower, kam durable. Yeh akela idea modern SSD capacity/endurance tradeoffs ka zyaadatar hissa explain karta hai.

Common mistakes

Forecast-then-Verify

Answer: chhota, kyunki $\Delta V_T=-Q_{FG}/C_{CG}$, $C_{CG}$ ke inversely proportional hai. Bada coupling capacitance usi trapped charge ko ek chhoti voltage swing mein "dilute" kar deta hai — yeh ek real design tension hai achhe control-gate coupling (${\alpha }_G$) aur bade sensing margin ke beech.

Flashcards

Connections

• MOSFET operation — FG cell sirf ek modified gate wala MOSFET hai; pehle $V_T$ samjho.
• Fowler-Nordheim tunneling — woh quantum mechanism jo NAND cells erase karta hai.
• Channel hot-electron injection — woh mechanism jo FG NAND (aur NOR) program karta hai.
• NAND vs NOR Flash architecture — FG cells arrays mein kaise wire hote hain.
• Multi-level cell (MLC TLC QLC) — continuous $\Delta V_T$ ka fayda uthana.
• Charge trap flash and 3D NAND — woh successor jo conductive FG ko insulating trap layer se replace karta hai.
• EEPROM and EPROM — pehle ke devices jo usi principle use karte hain.

Concept Map