4.1.8
Intuition Ek-sentence pictureFlash memory bits ko trapped electrons ke roop mein ek insulated gate par store karta hai. NOR cells ko is tarah wire karta hai ki koi bhi single byte turant read ho sake (code ke liye great); NAND cells ko tight series strings mein wire karta hai taaki zyada bits per area pack ho sakein (bulk data storage ke liye great).
Definition Floating-gate transistorEk flash cell ek aisa MOSFET hai jisme ek extra floating gate hota hai jo control gate aur channel ke beech daba hota hai, insulating oxide mein wrapped. Is floating gate par push kiye gaye electrons wahan saalon tak rehte hain (kyunki ye electrically isolated hai), aur transistor ki threshold voltage V t h
WHY ye non-volatile hai: floating gate oxide se ghira hua hai, isliye trapped charge ke paas leak hone ki jagah nahi hai. Data rakhne ke liye koi power nahi chahiye.
HOW ek bit encode hoti hai:
Floating gate par charge ⇒ high V t h 0 read hota hai.
Koi charge nahi ⇒ low V t h 1 read hota hai (ye "erased" state hai).
Intuition Threshold shift = poori ideaFloating gate ko ek chhota electron bucket socho jo switch aur us wire ke beech baitha hai jo use flip karta hai. Bucket bhar do, aur switch flip karne ke liye bahut bada push (control voltage) chahiye hoga. Hum electrons directly measure nahi karte — hum measure karte hain ki transistor on karna kitna mushkil hai .
Definition Program vs Erase mechanisms
Program (write 0): electrons ko floating gate par push karo. NAND Fowler–Nordheim (FN) tunnelling use karta hai; NOR classically channel hot-electron injection use karta hai.Erase (wapas 1 par): FN tunnelling ke zariye electrons ko pull off karo — ye poore ek block par ek saath hota hai.
Key asymmetry jo yaad rakhni chahiye:
Aap individual pages program kar sakte ho (1→0 selectively set karo).
Aap sirf poore blocks erase kar sakte ho (0→1 bulk mein reset karo).
Aap ek single bit ko 0→1 nahi flip kar sakte bina uske pore block ko erase kiye.
Ye flash ki defining constraint hai aur har flash filesystem / FTL design ko drive karti hai.
Har cell seedha ek bit line aur ground ke beech, parallel mein connect hota hai. Kisi bhi cell ko akele address karke read kiya ja sakta hai → sachchi random access , fast reads, byte addressable.
Cells ek bit-line contact share karte hue series mein strings mein connect hote hain (typically 32–128+ cells). Isse contact/wiring overhead khatam hoti hai → sabse chhota cell area, cheapest per bit, lekin poori ek page ek saath read karni padti hai.
NOR: ek bit line low pull hoti hai agar koi bhi selected cell conduct kare — jaise ek wired-OR / NOR logic structure. Har cell independently reachable hai ⇒ fast random read.NAND: ek string mein ek cell sense karne ke liye, baaki sab fully on hone chahiye (pass mode mein daalo). Output puri series chain par depend karta hai — jaise NAND logic. Kam contacts ⇒ denser.
Density aur zyada multiply hoti hai har cell mein kai bits store karke (V t h
Definition Endurance (P/E cycles)Har program/erase cycle oxide ko stress karta hai (FN tunnelling use se ghista hai). Cells ek limited number of Program/Erase (P/E) cycles ke baad oxide degradation ki wajah se unreliable ho jaate hain. Endurance mein SLC ≫ MLC ≫ TLC ≫ QLC.
Intuition Wear leveling — isliye controllers exist karte hainKyunki blocks kaafi P/E cycles ke baad kharab ho jaate hain aur erase sirf blocks mein hota hai, ek controller (the FTL , Flash Translation Layer) writes ko sab blocks mein spread karta hai taaki koi single block jaldi wear out na ho. Isliye ek SSD sirf "NAND nahi" hai.
Property
NOR NAND
Cell wiring
parallel (per-cell contact)
series strings
Cell size
~10 F 2
~4 F 2
Read
fast, random / byte
slower, page
Write/erase
slow
faster program, block erase
Random access
✅ execute-in-place (XIP)
❌ (page load karna padta hai)
Cost / bit
high
low
Typical use
boot/firmware code (BIOS)
SSDs, USB, SD, phones
Bits/cell
usually SLC
SLC→QLC
Worked example 1 — Voltage levels se bits per cellEk TLC cell apni V t h Ye step kyun: har distinguishable level ek symbol hai; bits = log 2 b = log 2 8 = 3 bits. Kyun matter karta hai: ek cell mein 3 bits = same silicon mein SLC ki 3× raw capacity.
Worked example 2 — Density comparisonSame process par, same area mein NAND mein NOR se kitne zyada cells fit hote hain?
Ye step kyun: per cell areas ka ratio.
A NAND A NOR = 4 F 2 10 F 2 = 2.5 × . 3 × 7.5 ×
Worked example 3 — Kyun ek byte in place edit nahi ho saktaEk file ek 256 KB block ke andar ek 4 KB page mein 1 byte use karti hai. Aap wo byte change karte ho.
Ye step kyun: flash sirf bits 0→1 clear kar sakta hai poore block ko erase karke.
Controller ko karna hoga: poora block read karo → byte ko RAM mein modify karo → block erase karo → rewrite karo (ya ek fresh block mein likho aur remap karo). Ek byte badla ⇒ 256 KB erase/write. Ye "write amplification" NAND ki intrinsic property hai.
Common mistake "Flash RAM ki tarah koi bhi single bit rewrite kar sakta hai."Kyun sahi lagta hai: reads hain random-access, isliye writes bhi aisi lagti hain.
Fix: programming sirf bits 1→0 selectively push kar sakti hai; 0→1 ke liye block erase chahiye. Writes page-granular hote hain, erases block-granular. Kabhi bhi bit-granular nahi.
Common mistake "NAND bas fast NOR hai."Kyun sahi lagta hai: NAND flash SSDs overall super fast hote hain.
Fix: NOR ke random reads faster hote hain aur ye execute-in-place support karta hai. NAND density, cost, aur sequential/page throughput mein jeet jaata hai, random-byte latency mein nahi. Dono alag-alag kaam ke liye hain.
Common mistake "Zyada bits per cell (QLC) strictly better hai."Kyun sahi lagta hai: per cell zyada capacity sunne mein pure win lagta hai.
Fix: zyada V t h
Common mistake "Gate par charge = 1."Kyun sahi lagta hai: "kuch store karna" 1 store karna feel hota hai.
Fix: convention inverted hai — charged (high V t h 0 ; erased/empty = 1 . Erase sab kuch 1s par reset karta hai.
Recall Feynman: ek 12-saal ke bacche ko samjhaoSocho ek light switch jisme andar ek chhota bucket chhupa hai. Normally ek chhoti si push switch on flip karti hai. Lekin agar tum bucket ko marbles (electrons) se bhar do, to switch "heavy" ho jaata hai aur use ek bahut bada push chahiye — to normal push par ye OFF rehta hai. Wo OFF matlab "0" hai, khali bucket matlab "1" hai. Marbles nikal nahi sakte kyunki bucket sealed hai, isliye power off hone par bhi yaad rehta hai. NOR har switch ko apna wire deta hai taaki koi bhi ek turant check ho sake. NAND switches ko ek row mein line up karta hai jo ek wire share karte hain — sasta hai aur bahut zyada fit ho jaate hain, lekin ek check karne ke liye baaki sab ko force on karna padta hai aur puri row ek saath read karni padti hai.
Flash cell mein charge kaunsa structure store karta hai? Floating gate (ek insulated gate jo control gate aur channel ke beech hota hai).
Charged floating gate konsa bit read karta hai? 0 (high threshold voltage, cell conduct nahi karta).
Reads ke liye byte/random addressable kaun hai: NOR ya NAND? NOR.
Chhota cell area (~4F²) aur lower cost/bit kaun deta hai? NAND.
Ek single flash bit 0→1 rewrite kyun nahi ho sakti? 0→1 ke liye erasing chahiye, aur erase sirf poore block par hota hai.
Write granularity vs erase granularity? Program = page; erase = block.
NAND program/erase ke liye kaunsa mechanism use karta hai? Fowler–Nordheim tunnelling.
TLC ke liye bits per cell aur kaise derive hua? 3 bits, log2(8 levels) se.
QLC, SLC se kam durable kyun hai? Zyada voltage levels squeezed in → chhoti margins → kam P/E cycles aur zyada errors.
FTL kya karta hai aur kyun? Logical ko physical blocks se map karta hai aur writes wear-level karta hai kyunki blocks limited P/E cycles ke baad kharab ho jaate hain.
NOR flash ka typical use kya hai? Boot code / firmware (execute-in-place, e.g. BIOS).
"Execute-in-place (XIP)" ke liye kya chahiye aur kaun sa flash support karta hai? Code ka random byte read → NOR.
Mnemonic Roles yaad rakhoN OR = N imble O n R andom reads → code chalata hai. NAND = N eeds A N ice D ense pack → data storage. Aur "Ch arged = Ch ero (zero)": charge stored → 0.
MOSFET and threshold voltage — wo physical device jis par flash bana hai.Non-volatile memory — flash ki family (volatile RAM ke vs).Solid State Drives (SSD) — NAND + FTL controller se bana hai.Fowler–Nordheim tunnelling — program/erase ki physics.Wear leveling and write amplification — block erase ke consequences.Memory hierarchy — flash kahan baithta hai (RAM ke neeche, disk ke upar).DRAM refresh — contrast: DRAM leak karta hai aur refresh chahiye; flash retain karta hai.
Channel hot-electron injection
