Row - column addressing and sense amplifiers

Chapter: Memory Technologies — how a chip finds ONE bit among millions, and how it reads a signal so tiny it can barely be measured.

The Core Problem (WHY this exists)

WHAT: The Anatomy

Figure — Row - column addressing and sense amplifiers

HOW: Why decoders shrink the pin count

Derivation — pins needed. Suppose the array holds $N = R \times C$ bits.

To pick 1 of $R$ rows you need $\log_2 R$ address bits.
To pick 1 of $C$ columns you need $\log_2 C$ address bits.
Total address bits: $\log_2 R + \log_2 C = \log_2(RC) = \log_2 N$ .

$\boxed{\text{address pins} = \log_2 N}$

Why this step? Each independent binary bit doubles how many lines you can name, so the number of things you can address is $2^{(\text{bits})}$ ; inverting gives $\log_2$ .

Square array minimizes pins-per-side. To split $\log_2 N$ address bits into row + column, and if we further want to time-multiplex the same pins for row then column (as real DRAM does with RAS/CAS), the pin count for one shared bus is minimized when $R = C = \sqrt N$ :

$\text{shared address pins} = \tfrac{1}{2}\log_2 N = \log_2\sqrt{N}.$

HOW: Reading a DRAM cell, step by step

Derivation — the sense voltage. Before the read, the bitline is precharged to $V_{DD}/2$ and then floated. The storage cell holds either $V_{DD}$ (logic 1) or $0$ (logic 0).

When the wordline turns on, cell and bitline share charge. Total charge before = charge after, using $Q = CV$ :

$C_s V_{cell} + C_b \cdot \tfrac{V_{DD}}{2} = (C_s + C_b)\,V_{final}$

Solve for the final bitline voltage:

$V_{final} = \frac{C_s V_{cell} + C_b \tfrac{V_{DD}}{2}}{C_s + C_b}$

The signal the sense amp sees is the deviation from the precharge point $V_{DD}/2$ :

$\Delta V = V_{final} - \frac{V_{DD}}{2} = \frac{C_s}{C_s + C_b}\left(V_{cell} - \frac{V_{DD}}{2}\right)$

Why this step? Subtracting the reference isolates only the part caused by the cell; everything common to the reference bitline cancels.

The sense amplifier's job (differential):

Precharge bitline (BL) and its complement ( $\overline{\text{BL}}$ ) to $V_{DD}/2$ .
Activate wordline → BL nudges up or down by $\Delta V$ ; $\overline{\text{BL}}$ stays at reference (or vice-versa, using a dummy cell).
Enable the cross-coupled latch (two back-to-back inverters). Positive feedback drives whichever line is higher to $V_{DD}$ and the other to $0$ .
Restore/refresh: the now-full-swing BL is still connected to the cell through the open access transistor, so the cell's capacitor is recharged to its original value. (Reading DRAM is destructive; the sense amp repairs it.)

Common Mistakes (Steel-manned)

Recall Explain it to a 12-year-old (click to reveal)

Think of a huge apartment building where every apartment holds a single drop of water (that's the memory bit). You can't run a pipe to every apartment — there are billions. So instead you say "Floor 12" (that turns on the whole floor's hallway light = wordline) and "Apartment 8" (that's the column pick). Now the tiny water drop trickles into a very long empty pipe (the bitline) and almost disappears. A special helper at the bottom of the pipe (the sense amplifier) is so sensitive it can tell "there WAS a drop" versus "there was NONE", shouts it loudly so everyone hears (full 0 or 1), and then — because looking used up the drop — pours the drop back into the apartment so it isn't lost. That last pour-back is why we say reading this memory erases it unless you refill it.

Flashcards

Why are memory cells arranged in a 2D grid instead of a line?

To share wires — a grid needs only

\log_2 R + \log_2 C

address bits instead of one wire per cell, making billion-bit chips feasible.

What does the row decoder physically do?

Takes the row address bits and raises exactly one wordline high, turning on the access transistors of every cell in that row.

What is a wordline vs a bitline?

Wordline = horizontal row-select control wire; Bitline = vertical column data wire shared by all cells in that column.

Why is a sense amplifier needed in DRAM?

The cell's charge shared onto the large bitline produces only tens of mV; the sense amp amplifies this tiny swing to a full logic level.

Give the charge-sharing sense-signal formula.

\Delta V = \dfrac{C_s}{C_s+C_b}\left(V_{cell}-\tfrac{V_{DD}}{2}\right)

Why precharge bitlines to

V_{DD}/2

It makes the read signal symmetric (

\pm\Delta V

) for 0 and 1, needs smaller swing to resolve, and enables differential sensing.

What are RAS and CAS?

Row Address Strobe and Column Address Strobe — latch the row then the column address on the SAME multiplexed pins.

How many address pins (multiplexed, square array) for

N

bits?

\tfrac12\log_2 N

Why is a DRAM read called destructive?

Connecting the cell to the bitline shares away its charge, losing the original value; the sense amp must write it back.

Why not just make the storage capacitor

C_s

very large?

Signal

\Delta V

saturates as

C_s\to C_b

, but big

C_s

wastes area and kills density; instead keep bitlines short.

What resolves the tiny signal to full swing inside a sense amp?

A cross-coupled inverter latch using positive feedback drives the higher line to

V_{DD}

and the other to

0

Connections

DRAM cell structure (1T1C) — the source of the tiny charge $C_s$ .
Memory refresh and retention time — why sense amps write back / how often.
SRAM 6T cell — non-destructive read, no refresh needed, contrast the sensing.
Address decoders and multiplexers — the $n\!\to\!2^n$ logic behind row/column select.
Memory banking and interleaving — splitting arrays to keep $C_b$ small.
CAS latency and memory timing — timing built on RAS/CAS multiplexing.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Socho ek bahut badi memory chip hai jisme crore-crore bits hain. Har bit ko alag wire dena impossible hai. Isliye cells ko ek grid (rows aur columns) me arrange karte hain. Ek particular bit tak pahunchne ke liye hum bolte hain "Row number itna, Column number itna" — bilkul stadium me seat dhoondhne jaisa. Row decoder sirf ek wordline ko high karta hai (us row ke saare cells ka gate ON), aur column decoder ek bitline ko output se jodta hai. Selected cell wahi hai jahan selected row aur selected column milte hain.

Ab problem: DRAM me har bit ek chhote capacitor $C_s$ par charge ke roop me stored hota hai. Jab wordline ON hota hai, ye chhota charge ek bahut lambi bitline (jiska apna bada capacitance $C_b$ ) par phail jaata hai. Formula $\Delta V=\frac{C_s}{C_s+C_b}(V_{cell}-V_{DD}/2)$ batata hai ki signal sirf kuch millivolt hi milega, kyunki $C_b$ , $C_s$ se bahut bada hota hai. Itna chhota signal koi normal logic gate padh hi nahi sakta.

Isiliye aata hai hero — sense amplifier. Pehle bitline ko $V_{DD}/2$ par precharge karte hain (taaki 0 aur 1 dono ke liye signal symmetric mile, $+\Delta V$ ya $-\Delta V$ ). Phir cross-coupled latch positive feedback se us chhote nudge ko full $V_{DD}$ ya $0$ tak amplify kar deta hai. Aur kyunki padhne me cell ka charge bik gaya (destructive read), sense amp usko wapas write-back / refresh bhi karta hai.

Yaad rakhne wali baat: DRAM address ko RAS (row pehle) aur CAS (column baad me) se, wahi pins reuse karke bhejta hai — isse pins aadhe ho jaate hain. Square array ( $R=C=\sqrt N$ ) sabse kam pins deता hai: $\frac12\log_2 N$ . Ye pura khel density aur speed ka balance hai — yahi reason hai ki aapka RAM sasta aur bada dono ho paata hai.

Row - column addressing and sense amplifiers

The Core Problem (WHY this exists)

WHAT: The Anatomy

HOW: Why decoders shrink the pin count

HOW: Reading a DRAM cell, step by step

Common Mistakes (Steel-manned)

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Memory Technologies

Connections