Row - column addressing and sense amplifiers: Worked examples

This page is the drill ground for the parent topic. We enumerate every kind of case the topic can throw at you — big signals, tiny signals, stored 0 vs stored 1, degenerate capacitors, non-square arrays, a real-world timing question — then work each one from scratch. Guess before you read the steps; that is where the learning happens.

Prerequisites you may want open: DRAM cell structure (1T1C), Address decoders and multiplexers, CAS latency and memory timing.

The scenario matrix

Two independent machines live in this topic:

The addressing machine (decoders): turns an address into a chosen wordline + bitline. Its "inputs" are array shapes.
The sensing machine (charge sharing + latch): turns tiny charge into a clean bit. Its "inputs" are the capacitor sizes and the stored voltage.

Every exam question is one cell of this table:

#	Machine	Case class	What makes it tricky	Example
A	Addressing	Square array, multiplexed pins	baseline	Ex 1
B	Addressing	Non-square array	$max (\cdot)$ dominates	Ex 2
C	Addressing	Degenerate: single row ( $R = 1$ )	column-only, limiting case	Ex 3
D	Sensing	Stored 1, normal $C_{b} ≫ C_{s}$	positive $Δ V$	Ex 4
E	Sensing	Stored 0, normal $C_{b} ≫ C_{s}$	negative $Δ V$ , symmetry	Ex 4
F	Sensing	Limiting: $C_{b} \to \infty$ (huge bitline)	signal collapses	Ex 5
G	Sensing	Degenerate: $C_{s} = C_{b}$ (equal caps)	signal saturates	Ex 6
H	Sensing	Sign edge: cell exactly at $V_{D D} /2$	zero signal — unreadable	Ex 7
I	Real-world	Refresh + retention word problem	leakage vs sense floor	Ex 8
J	Exam twist	Given $Δ V$ , solve backward for $C_{b}$	invert the formula	Ex 9

The two formulas we reuse everywhere, from the parent note:

The figure below plots the first formula for a fixed-size chip so you can see why square arrays win — refer back to it during Ex 1 and Ex 2.

Figure — Row - column addressing and sense amplifiers

Read the curve like this: the horizontal axis is how many address bits we spend on rows (the rest go to columns); the teal curve is the multiplexed pin count $max (row bits, col bits)$ . The plum dot at the bottom is the square array — the single lowest point — and the orange dashed line marks that optimum of 14 pins. Everything to the left or right (lopsided arrays) sits higher: more pins for the same chip.

Addressing examples (cells A, B, C)

Worked example Ex 1 — Cell A: a square 256 Mbit chip

A DRAM holds $N = 256$ Mbit $= 2^{28}$ bits, arranged as a square grid, address pins reused for row then column. How many address pins?

Forecast: guess a number 1–30 before reading on.

Find total bits as a power of two. $256 Mbit = 256 \times 2^{20} = 2^{8} \times 2^{20} = 2^{28}$ , so $N = 2^{28}$ . Why this step? The pin formula wants $lo g_{2} N$ , and that is trivial once $N$ is written as $2^{something}$ .
Split into a square grid. Square means $R = C = N = 2^{28} = 2^{14} = 16384$ rows and columns. This is the plum dot in the figure above. Why this step? A square array lets the SAME pins carry the row address then the column address (RAS then CAS), which is the whole point of multiplexing.
Count pins per phase. $lo g_{2} R = lo g_{2} 2^{14} = 14$ pins. Same for columns, but they share the wires. Why this step? $n$ pins name $2^{n}$ lines; inverting, $2^{14}$ lines need $14$ wires.
Apply the formula. $pins = \frac{1}{2} lo g_{2} N = \frac{1}{2} (28) = 14$ . Why this step? Because the row phase and the column phase reuse the same $14$ wires, the chip's pin count is one phase's width — the formula $\frac{1}{2} lo g_{2} N$ just packages "half the total address bits" into a single expression, confirming the per-phase count from step 3.

Answer: 14 address pins.

Verify: $14$ pins in phase 1 name $2^{14}$ rows, $14$ in phase 2 name $2^{14}$ columns → $2^{14} \times 2^{14} = 2^{28}$ cells. ✓ Matches $N$ . Without multiplexing you'd need $28$ pins — the reuse halved it.

Worked example Ex 2 — Cell B: a lopsided (non-square) array

Same $N = 2^{28}$ bits, but a lazy layout uses $R = 2^{20}$ rows and $C = 2^{8}$ columns. If row and column addresses are still multiplexed onto one shared bus, how many pins? This is a point off to the right on the figure above.

Forecast: more, fewer, or equal to Ex 1's 14?

Row address width: $lo g_{2} R = lo g_{2} 2^{20} = 20$ bits. Why this step? We need enough address bits to name every one of the $2^{20}$ rows independently, and $n$ bits name $2^{n}$ things — so naming $2^{20}$ rows takes exactly $20$ bits.
Column address width: $lo g_{2} C = lo g_{2} 2^{8} = 8$ bits. Why this step? Same logic applied to the other dimension: $2^{8}$ columns each need a unique name, and $8$ bits produce exactly $2^{8}$ distinct names.
Shared bus must fit the WIDER phase. $pins = max (20, 8) = 20$ . Why this step? The same physical wires carry both addresses at different times, so they must be wide enough for the larger of the two. The narrow phase just leaves some pins unused.

Answer: 20 pins — worse than the square array's 14.

Verify: the general fact $max (a, b) \geq \frac{a + b}{2}$ with equality only when $a = b$ . Here $\frac{20 + 8}{2} = 14$ (the square-optimal), and $max (20, 8) = 20 > 14$ . ✓ This is why designers push arrays toward square.

Worked example Ex 3 — Cell C: the degenerate single-row array (

$R = 1$ ) A tiny structure has $N = 16$ bits in one row of $16$ columns ( $R = 1$ , $C = 16$ ). It is not multiplexed (you supply row and column bits at once). How many address pins?

Forecast: does the row need any pins at all?

Row bits: $lo g_{2} R = lo g_{2} 1 = 0$ . Why this step? With one row there is nothing to choose — the "row decoder" is a wire that is always high. Choosing 1-of-1 needs zero information.
Column bits: $lo g_{2} C = lo g_{2} 16 = 4$ . Why this step? There are 16 columns to distinguish, and each address bit doubles how many columns we can name; naming 16 columns therefore takes $lo g_{2} 16 = 4$ bits.
Total (not multiplexed): $0 + 4 = 4$ pins. Why this step? Because the addresses are NOT time-shared, the row bits and column bits ride on separate wires simultaneously, so the pin count is their plain sum — not a $max$ .

Answer: 4 pins, all of them column bits.

Verify: $lo g_{2} N = lo g_{2} 16 = 4$ , and indeed row+column $= 0 + 4 = 4$ . ✓ The limiting case $R = 1$ turns a 2D memory back into the 1D line the parent note warned against — fine for 16 bits, catastrophic for a billion.

Sensing examples (cells D, E, F, G, H)

For all sensing examples we use a fixed chip unless stated: $V_{D D} = 1.2$ V, so the precharge mid-rail is $V_{D D} /2 = 0.6$ V.

The figure below plots the second formula: sense signal $Δ V$ against the stored cell voltage. Keep it in view for Ex 4 and Ex 7 — the straight line is the sensing physics.

Read it like this: the horizontal axis is what the cell holds, $V_{ce l l}$ ; the vertical axis is the resulting signal $Δ V$ in millivolts. The line crosses zero exactly at the mid-rail $0.6$ V (the black square). The orange dot at $V_{ce l l} = 1.2$ V is a stored 1 giving $+ 54.5$ mV; the plum dot at $V_{ce l l} = 0$ V is a stored 0 giving $- 54.5$ mV — equal and opposite, which is the whole reason for mid-rail precharge.

Worked example Ex 4 — Cells D & E: stored 1 vs stored 0, normal caps

$C_{s} = 20$ fF, $C_{b} = 200$ fF. Compute $Δ V$ for (D) a stored 1 ( $V_{ce l l} = 1.2$ V) and (E) a stored 0 ( $V_{ce l l} = 0$ V).

Forecast: will the two magnitudes be equal or different?

Compute the capacitance ratio once. $\frac{C _{s}}{C _{s} + C _{b}} = \frac{20}{20 + 200} = \frac{20}{220} = \frac{1}{11} \approx 0.0909$ . Why this step? This ratio is the "leverage" — how much of the cell's voltage difference survives onto the fat bitline. Compute it once, reuse for both cases.
Case D (stored 1): $Δ V = 0.0909 \times (1.2 - 0.6) = 0.0909 \times 0.6 = + 0.0545$ V $= + 54.5$ mV. Why this step? $V_{ce l l} - V_{D D} /2$ is positive, so the bitline nudges up off the mid-rail.
Case E (stored 0): $Δ V = 0.0909 \times (0 - 0.6) = 0.0909 \times (- 0.6) = - 0.0545$ V $= - 54.5$ mV. Why this step? Now the deviation term is negative — the bitline dips below mid-rail. The latch resolves "below reference" as logic 0.

Answer: +54.5 mV for a 1, −54.5 mV for a 0.

Verify: the magnitudes are identical, $∣ + 54.5 ∣ = ∣ - 54.5 ∣$ . ✓ That symmetry is exactly why we precharge to mid-rail — a stored 0 and a stored 1 give equal and opposite nudges, so one differential sense amp handles both cases with no bias.

Worked example Ex 5 — Cell F: the limiting case of a huge bitline (

$C_{b} \to \infty$ ) Keep $C_{s} = 20$ fF, stored 1. What happens to $Δ V$ as the bitline grows: $C_{b} = 200$ fF, then $2000$ fF, then $\to \infty$ ?

Forecast: does the signal shrink toward some value?

$C_{b} = 200$ fF: ratio $= 20/220 = 0.0909$ , $Δ V = 54.5$ mV (from Ex 4). Why this step? We re-evaluate $C_{s} / (C_{s} + C_{b})$ at each bitline size because the ratio is the ONLY part of the formula that changes here ( $C_{s}$ and $V_{ce l l}$ are fixed) — so tracking the ratio is tracking the signal.
$C_{b} = 2000$ fF: ratio $= 20/2020 = 0.0099$ , $Δ V = 0.0099 \times 0.6 = 5.94$ mV. Why this step? Ten times more bitline capacitance means the cell's charge is diluted into ten times the "bucket" — the signal drops roughly tenfold.
Limit $C_{b} \to \infty$ : $\frac{C _{s}}{C _{s} + C _{b}} \to \frac{C _{s}}{C _{b}} \to 0$ , so $Δ V \to 0$ . Why this step? An infinitely long bitline swallows the cell's charge with no measurable voltage change — the cell's whisper is lost in an ocean.

Answer: signal falls toward 0 as the bitline lengthens.

Verify: $5.94$ mV is about one-tenth of $54.5$ mV, matching the 10× capacitance jump. ✓ This is the physics behind the parent note's advice: split arrays into sub-banks to keep bitlines short (see Memory banking and interleaving).

Worked example Ex 6 — Cell G: degenerate equal capacitors (

$C_{s} = C_{b}$ ) Suppose fabrication went wrong and $C_{s} = C_{b} = 100$ fF. Stored 1, $V_{D D} = 1.2$ V. Compute $Δ V$ and interpret.

Forecast: will the ratio be bigger than the usual $\approx 0.09$ ?

Ratio: $\frac{C _{s}}{C _{s} + C _{b}} = \frac{100}{100 + 100} = \frac{1}{2} = 0.5$ . Why this step? When the two capacitors are equal, they split the charge evenly — the cell keeps half its voltage difference, the bitline gets the other half.
Signal: $Δ V = 0.5 \times (1.2 - 0.6) = 0.5 \times 0.6 = 0.3$ V $= 300$ mV. Why this step? Plug the ratio straight in. This is a giant signal — trivially readable.
Interpret the saturation. The ratio $\frac{C _{s}}{C _{s} + C _{b}}$ can never exceed 1, and reaches $0.5$ already at $C_{s} = C_{b}$ . Making $C_{s}$ even bigger buys almost nothing more but destroys density. Why this step? This is the steel-manned mistake from the parent: "make $C_{s}$ huge." The signal saturates; area does not.

Answer: 300 mV — easy to sense, but a density disaster.

Verify: at $C_{s} = C_{b}$ the ratio is exactly $0.5$ , so $Δ V = V_{D D} /4 = 1.2/4 = 0.3$ V. ✓

Worked example Ex 7 — Cell H: the sign edge — a half-charged cell (

$V_{ce l l} = V_{D D} /2$ ) A leaky cell has decayed until $V_{ce l l} = 0.6$ V, exactly mid-rail, with $C_{s} = 20$ fF, $C_{b} = 200$ fF. What signal does the sense amp see?

Forecast: positive, negative, or zero?

Deviation term: $V_{ce l l} - V_{D D} /2 = 0.6 - 0.6 = 0$ . Why this step? The signal is driven entirely by how far the cell sits from mid-rail. If it sits exactly on mid-rail, there is nothing to detect.
Signal: $Δ V = 0.0909 \times 0 = 0$ V. Why this step? Zero times any ratio is zero — the sense amp gets no nudge in either direction.

Answer: $Δ V = 0$ — the bit is genuinely unreadable at this instant.

Verify: $Δ V = 0$ regardless of $C_{s}, C_{b}$ when $V_{ce l l} = V_{D D} /2$ . ✓ This is the danger zone: as a cell leaks toward mid-rail, its signal shrinks to nothing. That is precisely what Memory refresh and retention time must prevent — refresh before the cell drifts here.

Real-world & exam-twist examples (cells I, J)

Worked example Ex 8 — Cell I: refresh timing word problem

A cell starts a fresh 1 at $V_{ce l l} = 1.2$ V and leaks toward $0.6$ V at a steady $6$ mV per millisecond. The sense amp needs at least $Δ V = 20$ mV to reliably resolve the bit. With $C_{s} = 20$ fF, $C_{b} = 200$ fF, what is the longest safe refresh interval?

Forecast: guess whether it's closer to 1 ms or 100 ms.

Find the minimum readable $V_{ce l l}$ . Set $Δ V = 20$ mV and solve $V_{ce l l}$ from $Δ V = \frac{C _{s}}{C _{s} + C _{b}} (V_{ce l l} - 0.6)$ . With ratio $0.0909$ : $0.020 = 0.0909 (V_{ce l l} - 0.6)$ . Why this step? The retention limit is the moment the signal drops to the sense floor; below that the bit is lost.
Solve for $V_{ce l l}$ . $V_{ce l l} - 0.6 = 0.020/0.0909 = 0.22$ V, so $V_{ce l l} = 0.82$ V. Why this step? This is the lowest cell voltage the amp can still call a "1".
Voltage budget to burn. From the fresh $1.2$ V down to $0.82$ V is $1.2 - 0.82 = 0.38$ V $= 380$ mV. Why this step? That's how much the cell may leak before hitting the floor — the total voltage headroom we get to spend.
Divide budget by the leak rate. $t = \frac{380 mV}{6 mV/ms} \approx 63.3 ms$ . Why this step? Time = (voltage to lose) ÷ (voltage lost per unit time). Units check: $mV \div (mV/ms) = ms$ . ✓

Answer: refresh at least every ≈ 63.3 ms.

Verify: at $V_{ce l l} = 0.82$ V, $Δ V = 0.0909 \times (0.82 - 0.6) = 0.0909 \times 0.22 = 0.020$ V $= 20$ mV — exactly the sense floor. ✓ Real DRAM uses ~64 ms, reassuringly close.

Worked example Ex 9 — Cell J: the backward exam twist — solve for

$C_{b}$ Exam question: "A cell with $C_{s} = 30$ fF stores a 1 at $V_{D D} = 1.2$ V. Measured $Δ V = 40$ mV. What is the bitline capacitance $C_{b}$ ?"

Forecast: bigger or smaller than a typical $250$ fF?

Write the known deviation. $V_{ce l l} - V_{D D} /2 = 1.2 - 0.6 = 0.6$ V. Why this step? The deviation term is the only fully-known piece on the right-hand side, so pinning it down first collapses the equation to a single unknown ratio — which we can then invert for $C_{b}$ .
Isolate the ratio. From $0.040 = \frac{C _{s}}{C _{s} + C _{b}} (0.6)$ , the ratio $\frac{C _{s}}{C _{s} + C _{b}} = \frac{0.040}{0.6} = 0.0667$ . Why this step? We can't get $C_{b}$ directly, but the ratio is one clean number we can back out first.
Invert the ratio for $C_{b}$ . $\frac{C _{s}}{C _{s} + C _{b}} = 0.0667 \Rightarrow C_{s} + C_{b} = \frac{C _{s}}{0.0667} = \frac{30}{0.0667} = 450$ fF, so $C_{b} = 450 - 30 = 420$ fF. Why this step? Cross-multiplying turns the ratio equation into a plain subtraction for $C_{b}$ .

Answer: $C_{b} = 420$ fF.

Verify: plug back — $Δ V = \frac{30}{30 + 420} (0.6) = \frac{30}{450} (0.6) = 0.0667 \times 0.6 = 0.040$ V $= 40$ mV. ✓ Larger than a nice $250$ fF, meaning this bitline is uncomfortably long — a hint the array should be sub-banked.

Recall Quick self-test (click to reveal)

Non-square $2^{28}$ -bit array with $R = 2^{20}$ needs how many multiplexed pins? ::: $max (20, 8) = 20$ . Why precharge to $V_{D D} /2$ and not $V_{D D}$ ? ::: It makes stored 0 and stored 1 give equal and opposite $Δ V$ , so one differential amp reads both symmetrically. A cell at exactly $V_{D D} /2$ gives what signal? ::: $Δ V = 0$ — unreadable; refresh must act before the cell drifts this far. Doubling $C_{b}$ does what to $Δ V$ ? ::: Roughly halves it (dilutes the cell charge into a bigger bitline).