Row - column addressing and sense amplifiers: Question bank

A pure-reasoning question bank for the parent topic. No heavy arithmetic here — every item targets a misconception or a boundary case. Reveal each answer only after you've committed to your own reasoning.

Before you start, make sure these words feel solid: a wordline is the horizontal wire that switches ON a whole row of cells; a bitline is the vertical wire that carries one column's data; a sense amplifier is the tiny detector-and-restorer at the foot of each bitline; precharge means parking the bitline at a known middle voltage $V_{D D} /2$ before the read. If any of those is fuzzy, revisit DRAM cell structure (1T1C) and the parent note first.

True or false — justify

Every claim below is either true or false. Say which, then give the reason — the reason is the point, not the verdict.

A DRAM read destroys the stored bit, so the sense amp must write it back.

True. Connecting the tiny cell capacitor to the huge bitline shares its charge away, physically erasing the original level; the cross-coupled latch drives the line full-swing and, through the still-open access transistor, recharges the cell. This restore-on-read is why the bit survives.

The row decoder is the circuit that actually reads the data value out of a cell.

False. The decoder only raises one wordline — it selects, it never senses. The data appears because cells dump charge onto bitlines and the sense amplifiers detect and latch it.

n

-bit address bus can uniquely name

2^{n}

different cells.

True. Each independent binary bit doubles the number of nameable lines, so

n

bits name

2^{n}

things — that exponential compression is the entire reason huge memories need only a handful of address pins.

Precharging the bitline to

V_{D D}

(the logic-1 level) makes reads easier because a stored 1 needs no change.

False. Precharge to

V_{D D}

gives a stored 1 zero signal (no swing) and a stored 0 a full-swing drop — hopelessly asymmetric. Mid-rail

V_{D D} /2

gives

\pm Δ V

symmetric signal so a differential amp can compare BL against

\overline{BL}

Making the storage capacitor

C_{s}

much larger always gives a proportionally larger sense signal.

False.

Δ V = \frac{C _{s}}{C _{s} + C _{b}} (V_{ce l l} - \frac{V _{D D}}{2})

saturates: once

C_{s}

approaches

C_{b}

the fraction approaches 1 and extra capacitance buys almost no signal — only wasted area and lost density.

For the same chip, reading a stored 0 and reading a stored 1 produce sense signals of equal magnitude but opposite sign.

True. With mid-rail precharge,

V_{ce l l} - V_{D D} /2

+ V_{D D} /2

for a 1 and

- V_{D D} /2

for a 0 — equal size, opposite direction. That symmetry is exactly why mid-rail precharge is chosen.

Time-multiplexing the address pins (RAS then CAS) roughly halves the number of address pins on a square array.

True. Sending the row address then the column address on the same wires means you only need

max (lo g_{2} R, lo g_{2} C)

pins instead of

lo g_{2} R + lo g_{2} C

; for a square array that is exactly half. See CAS latency and memory timing for the time cost this trades against.

A larger bitline capacitance

C_{b}

helps the sense amplifier.

False.

C_{b}

is in the denominator of

Δ V

, so a bigger bitline load dilutes the cell's charge and shrinks the signal. Designers fight

C_{b}

by keeping bitlines short via sub-banking.

SRAM cells also need a periodic write-back after every read the way DRAM does.

False. An SRAM 6T cell holds its value in a latch that actively drives the bitlines, so a read is non-destructive and needs no refresh — that's a structural difference from the passive 1T1C DRAM cell.

Spot the error

Each statement contains one flaw. Name it and correct it.

"A cell is accessed as soon as its wordline goes high."

Incomplete: raising the wordline connects every cell in that row to its bitline. You isolate one cell only after the column multiplexer also selects that column's bitline — wordline AND bitline both.

"To pick 1 of 1024 rows you need 1024 address wires into the row decoder."

Wrong direction: the decoder's whole purpose is compression. You need

lo g_{2} 1024 = 10

input wires; the decoder expands them to 1024 wordlines, exactly one raised at a time. See Address decoders and multiplexers.

Δ V

is a few volts, which the logic gates read directly."

No — because

C_{b} ≫ C_{s}

(often

10

–

30 \times

Δ V

is only tens of millivolts, far below a clean logic level. That tiny nudge is why a sense amplifier exists: to blow it up to full rail.

"The sense amp measures the absolute voltage on the bitline to decide 0 or 1."

A differential sense amp doesn't read an absolute level; it compares BL against a reference line

\overline{BL}

held at

V_{D D} /2

and latches whichever is higher. Comparison rejects noise common to both lines.

"You can precharge the bitline once at power-on and leave it."

The bitline must be re-precharged to

V_{D D} /2

before every read, because the previous read left it driven to full rail. Skipping precharge means the latch starts from a lopsided state and can resolve the wrong way.

"A perfectly square array is optimal only because it looks neat."

The square shape (

R = C = N

) minimizes the shared address-pin count under RAS/CAS multiplexing: it makes

max (lo g_{2} R, lo g_{2} C)

as small as possible. A lopsided

2^{16} \times 2^{4}

array would force 16 pins instead of 10.

Why questions

Answer the reason, not just the fact.

Why are cells arranged in a 2D grid instead of a single long line?

A line of

N

cells would need addressing hardware and wiring that scale with

N

directly; a

N \times N

grid lets a row decoder and a column decoder each handle only

N

lines, and lets the address pins be reused across two phases — massively fewer pins and shorter wires.

Why precharge to the midpoint

V_{D D} /2

specifically, and not some other level?

Mid-rail sits exactly between a stored 0 and a stored 1, so the cell's charge pushes the bitline up or down by the same amount either way. Equal-and-opposite signal lets one symmetric differential amp resolve both cases with the smallest possible swing.

Why must the access transistor stay ON during the restore phase?

Because restore works by letting the full-swing bitline drive charge back into the cell through that transistor. If it closed early, the latch would still show the right value on the bitline but the cell capacitor would remain half-emptied and lose the bit.

Why does keeping

C_{s}

small actually help the overall chip, despite giving a weaker signal?

A small

C_{s}

means a small cell, which means higher density — the entire economic reason DRAM exists. The signal loss is recovered by keeping

C_{b}

small (short bitlines) rather than by growing every cell.

Why can the sense amplifier tolerate a signal as small as tens of millivolts?

The cross-coupled inverter latch is a positive-feedback element: any tiny imbalance makes each inverter push the other harder, and the loop runs away until one line hits

V_{D D}

and the other

0

. It doesn't need a big input, only a definite direction.

Why does a stored 1 make the bitline rise while a stored 0 makes it fall?

Precharge parks BL at

V_{D D} /2

. A cell at

V_{D D}

(a 1) is above that reference, so charge sharing pulls BL up (

Δ V > 0

); a cell at

0

is below it, so BL is pulled down (

Δ V < 0

). The sign of

V_{ce l l} - V_{D D} /2

sets the direction.

Why does DRAM need periodic refresh at all, and how is a read connected to it?

The 1T1C cell's charge leaks away over milliseconds (see Memory refresh and retention time), so it must be rewritten periodically. A read already ends in a restore, so refresh is often implemented as simply reading every row on a schedule — the sense amp's write-back doubles as the refresh.

Edge cases

Boundary and degenerate scenarios the topic quietly invites.

What is the sense signal

Δ V

when the stored cell voltage happens to equal

V_{D D} /2

exactly?

Δ V = 0

: the cell is already at the reference, so charge sharing moves the bitline nowhere and the latch has no direction to fall. This is precisely the forbidden leaked-halfway state — the retention margin exists to keep real cells away from it.

In the limiting case

C_{s} ≫ C_{b}

(imaginary huge cell), what does

Δ V

approach?

The fraction

\frac{C _{s}}{C _{s} + C _{b}} \to 1

, so

Δ V \to V_{ce l l} - V_{D D} /2

, i.e. the full half-rail swing. This shows the formula's ceiling: you can never get more than half of

V_{D D}

of signal, no matter how big the cell.

In the opposite limit

C_{b} ≫ C_{s}

(very long bitline), what happens to the signal?

\frac{C _{s}}{C _{s} + C _{b}} \to 0

, so

Δ V \to 0

— the cell's charge is drowned in the bitline's capacitance and no readable signal survives. This is the hard physical limit on how long a bitline can be before the array must be split.

What happens if two wordlines in the same array are raised simultaneously?

Two cells in the same column would both dump onto one bitline, mixing their charges — the sense amp sees a scrambled average and both stored bits are corrupted. The decoder is built to raise exactly one wordline for this reason.

For a non-square array

R = 2^{16}, C = 2^{4}

holding the same

2^{20}

bits, how many multiplexed address pins are forced?

max (16, 4) = 16

pins — because RAS and CAS share the same wires, the pin count is set by the larger dimension. The square

2^{10} \times 2^{10}

layout needs only 10, showing why lopsided arrays waste pins.

What does the sense amp do on a column whose wordline was not raised this cycle?

That bitline stays at its precharge reference against

\overline{BL}

, so with no imbalance the latch, once enabled, resolves on noise alone — which is why only selected rows are activated and unselected bitlines are typically kept precharged or unlatched.

Recall One-line summary of every trap above

Decoders select, sense amps sense; the signal is tiny because $C_{b} ≫ C_{s}$ ; mid-rail precharge makes it symmetric; the latch's feedback amplifies direction not size; and every DRAM read ends in a restore because reading is destructive.