Row - column addressing and sense amplifiers: Exercises

This page is a self-test. Each problem states its difficulty level (L1 → L5). Try it first with the solution collapsed, then click to reveal. All the tools you need were built in the parent note: Row/Column Addressing and Sense Amplifiers.

Prerequisites you may want open: DRAM cell structure (1T1C), Address decoders and multiplexers, Memory banking and interleaving, CAS latency and memory timing.

L1 — Recognition

Problem 1 (L1)

A memory chip stores $N = 4, 194, 304$ bits. How many address bits are needed to name every bit uniquely (before we split them into rows and columns)?

Recall Solution 1

We need the smallest number of binary digits that can name $N$ distinct locations. Since $n$ bits name $2^{n}$ things, we invert: address bits $= lo g_{2} N$ .

$N = 4, 194, 304 = 2^{22}$ (because $2^{20} = 1, 048, 576$ and $\times 4 = 2^{22}$ ). $lo g_{2} N = 22 address bits .$ What it means: 22 wires can pick 1 cell out of over 4 million.

In a DRAM read, which wire is horizontal and turns on the access transistors of a whole row, and which is vertical and carries the data in/out? Name each and state which one the sense amplifier sits on.

Recall Solution 2

Horizontal control wire that turns on a row = wordline (driven by the row decoder).
Vertical data wire shared by a column = bitline.
The sense amplifier sits at the bottom of each bitline, because that is where the tiny charge-sharing signal appears.

Quick check: wordline selects, bitline carries, sense amp senses on the bitline.

L2 — Application

Problem 3 (L2)

A square DRAM array holds $N = 2^{24}$ bits. It multiplexes the row and column address onto the same pins (RAS then CAS). How many address pins does the chip expose?

Recall Solution 3

Square means $R = C = N = 2^{12}$ . Each phase needs $lo g_{2} R = lo g_{2} 2^{12} = 12$ bits. Since RAS and CAS reuse the same pins, the pin count is one phase's worth: $pins = \frac{1}{2} lo g_{2} N = \frac{1}{2} (24) = 12 pins .$ What it means: 12 physical pins, used twice, name $2^{24} \approx 16.7$ million bits.

Problem 4 (L2)

Using the sense-signal formula, compute $Δ V$ for a stored 1 with $V_{D D} = 1.0$ V, $C_{s} = 20$ fF, $C_{b} = 200$ fF.

Recall Solution 4

Stored 1 means $V_{ce l l} = V_{D D} = 1.0$ V. Precharge reference is $V_{D D} /2 = 0.5$ V. $Δ V = \frac{C _{s}}{C _{s} + C _{b}} (V_{ce l l} - \frac{V _{D D}}{2}) = \frac{20}{20 + 200} (1.0 - 0.5) .$ $Δ V = \frac{20}{220} (0.5) = 0.0909 \times 0.5 = 0.04545 V \approx 45.5 mV .$ What it means: the bitline rises only ~45 mV — invisible to a logic gate, hence the latch must amplify it.

Problem 5 (L2)

For the same chip as Problem 4, what is $Δ V$ when the cell stores a 0? What does the sign tell you?

Recall Solution 5

Stored 0 means $V_{ce l l} = 0$ . $Δ V = \frac{20}{220} (0 - 0.5) = 0.0909 \times (- 0.5) = - 0.04545 V \approx - 45.5 mV .$ The negative sign means the bitline dips below the $V_{D D} /2$ reference. The magnitude equals the stored-1 case — that symmetry is exactly why we precharge to mid-rail.

L3 — Analysis

Problem 6 (L3)

Take the midnight chip: $V_{D D} = 1.2$ V, $C_{s} = 25$ fF. A sense amplifier can only reliably resolve a signal of magnitude $\geq 50$ mV. What is the largest bitline capacitance $C_{b}$ the design can tolerate for a stored 1?

Recall Solution 6

Stored 1 gives $Δ V = \frac{C _{s}}{C _{s} + C _{b}} \cdot \frac{V _{D D}}{2}$ . Require $Δ V \geq 0.050$ V. $\frac{25}{25 + C _{b}} \cdot 0.6 \geq 0.050 \Rightarrow \frac{25}{25 + C _{b}} \geq \frac{0.050}{0.6} = 0.08333.$ Invert (flip inequality): $\frac{25 + C _{b}}{25} \leq 12.0$ , so $25 + C_{b} \leq 300$ , giving $C_{b} \leq 275 fF .$ What it means: to guarantee a readable signal, the bitline (with all the cells hanging off it) must present at most 275 fF — which is why long bitlines get split into sub-arrays.

Read the figure below: the blue curve is $Δ V$ falling as $C_{b}$ grows; the red dashed line is the 50 mV floor; the green dot is exactly where they cross, at $C_{b} = 275$ fF. Any $C_{b}$ to the right of the yellow line drops the signal below the floor — an unreadable bit.

Figure — Row - column addressing and sense amplifiers

Problem 7 (L3)

A 1 Mbit array ( $N = 2^{20}$ ) can be built as (a) square $R = C = 2^{10}$ , or (b) tall-and-thin $R = 2^{16}$ , $C = 2^{4}$ . For a multiplexed address bus, how many pins does each need, and which wins?

Recall Solution 7

Why the formula is $max (lo g_{2} R, lo g_{2} C)$ . A multiplexed bus is a single set of physical wires reused in two phases: RAS carries the row address ( $lo g_{2} R$ bits), then CAS carries the column address ( $lo g_{2} C$ bits) on the same wires. A wire that exists in phase 1 also exists in phase 2 — you cannot have "half a wire" for the narrower phase. So the number of wires must be large enough to hold whichever phase is wider; a bus of $max (lo g_{2} R, lo g_{2} C)$ wires can carry both, and anything smaller would drop bits of the wider phase. Hence pins $= max (lo g_{2} R, lo g_{2} C)$ .

(a) Square: $max (10, 10) = 10$ pins.
(b) Tall-thin: $max (16, 4) = 16$ pins.

The square array wins (10 pins vs 16). The maximum of two numbers with a fixed sum ( $lo g_{2} R + lo g_{2} C = 20$ ) is smallest when the two are equal — that is the mathematical reason square arrays are preferred for multiplexed addressing.

Problem 8 (L3)

A DRAM read is called destructive. Explain physically why, and state precisely which step of the sense amplifier's operation repairs it.

Recall Solution 8

Why destructive: activating the wordline connects the cell capacitor $C_{s}$ to the bitline $C_{b}$ . Charge redistributes so both settle to the same $V_{f ina l} = \frac{C _{s} V _{ce l l} + C _{b} ( V _{D D} /2 )}{C _{s} + C _{b}}$ . The cell no longer holds its original $V_{ce l l}$ — the stored value is physically gone. The repair: step 4 (Restore / refresh) of the four-step sequence defined at the top of this page. Once the cross-coupled latch drives the bitline to a full rail ( $V_{D D}$ or $0$ ) and the access transistor is still on, the cell capacitor is recharged through it back to the full original value. Reading therefore rewrites. (Related idea: Memory refresh and retention time.)

L4 — Synthesis

Problem 9 (L4)

You must design a square, multiplexed DRAM. Requirements: capacity $\geq 64$ Mbit, and the sense signal for a stored 1 must be $\geq 60$ mV with $V_{D D} = 1.1$ V, $C_{s} = 24$ fF, and a bitline capacitance that grows as $C_{b} = 0.5 fF \times (cells per bitline)$ . Find (a) the address-pin count and (b) verify the signal margin.

Recall Solution 9

(a) Capacity → geometry. Smallest square power-of-two array $\geq 64 Mbit = 2^{26}$ : take $N = 2^{26}$ , so $R = C = 2^{13} = 8192$ . Multiplexed pins: $pins = \frac{1}{2} lo g_{2} N = \frac{1}{2} (26) = 13 pins .$

(b) Signal check. Cells per bitline = number of rows = $R = 8192$ . So $C_{b} = 0.5 \times 8192 = 4096 fF .$ That is enormous vs $C_{s} = 24$ fF. Signal for a stored 1: $Δ V = \frac{24}{24 + 4096} \cdot \frac{1.1}{2} = \frac{24}{4120} (0.55) = 0.005825 \times 0.55 \approx 3.2 mV .$ Verdict: FAILS ( $3.2 mV ≪ 60 mV$ ). The single monolithic bitline is far too long. Fix — split the array. Break the 8192 rows into $k$ sub-arrays of $8192/ k$ rows each, each with its own sense amps, so $C_{b} = 0.5 \times (8192/ k)$ . Solve for the required $k$ : $\frac{24}{24 + 4096/ k} (0.55) \geq 0.060 \Rightarrow \frac{24}{24 + 4096/ k} \geq 0.10909.$ $24 + \frac{4096}{k} \leq 220.0 \Rightarrow \frac{4096}{k} \leq 196.0 \Rightarrow k \geq 20.9.$ So $k = 21$ sub-arrays (or, in practice, round to $k = 32$ , a power of two) makes each bitline short enough. This is exactly the banking / sub-array idea in Memory banking and interleaving.

L5 — Mastery

Problem 10 (L5)

A designer proposes precharging bitlines to $V_{D D}$ instead of $V_{D D} /2$ . Using the same chip as Problem 4 ( $V_{D D} = 1.0$ V, $C_{s} = 20$ fF, $C_{b} = 200$ fF), compute the read signal for a stored 1 and a stored 0 under this scheme, compare with the mid-rail scheme, and argue quantitatively why mid-rail wins.

Recall Solution 10

With precharge to $V_{r e f}$ , the general signal is $Δ V = \frac{C _{s}}{C _{s} + C _{b}} (V_{ce l l} - V_{r e f})$ . Here $\frac{C _{s}}{C _{s} + C _{b}} = \frac{20}{220} = 0.0909$ .

Precharge to $V_{D D} = 1.0$ V:

Stored 1: $Δ V = 0.0909 (1.0 - 1.0) = 0$ V. No signal at all — the sense amp cannot tell the bitline moved.
Stored 0: $Δ V = 0.0909 (0 - 1.0) = - 0.0909$ V $= - 90.9$ mV.

Precharge to $V_{D D} /2 = 0.5$ V (mid-rail):

Stored 1: $Δ V = 0.0909 (1.0 - 0.5) = + 45.5$ mV.
Stored 0: $Δ V = 0.0909 (0 - 0.5) = - 45.5$ mV.

Why mid-rail wins (quantitatively):

The $V_{D D}$ -precharge scheme gives $∣Δ V ∣ = 0$ for a stored 1 — a guaranteed read failure for half the data.
Mid-rail is symmetric: $\pm 45.5$ mV for 1 and 0. A differential sense amp comparing the bitline BL against its complement $\overline{BL}$ (both starting at $V_{D D} /2$ ) sees the same-magnitude nudge either way, so one threshold works for both and the worst-case swing to resolve is halved ( $45.5$ mV vs the $90.9$ mV worst case above).

Conclusion: mid-rail precharge is the only choice that gives a nonzero, symmetric signal for both logic values — the foundation of differential sensing.

Recall One-line summary you should be able to recite

Addressing shrinks pins via $lo g_{2}$ ; square + multiplex halves them; charge sharing gives a tiny $Δ V = \frac{C _{s}}{C _{s} + C _{b}} (V_{ce l l} - \frac{V _{D D}}{2})$ that only a mid-rail-precharged differential sense amp can resolve — and it rewrites the cell because the read destroyed it.

Exercises — Row - column addressing and sense amplifiers