Row - column addressing and sense amplifiers: Visual walkthrough

This page rebuilds ONE result from nothing: the tiny voltage $Δ V$ that a DRAM read produces on a bitline. We will see every charge move. By the end you will know exactly why the number is only tens of millivolts, why it can be positive or negative, and why the whole read scheme is built around one clever choice: precharging to the halfway voltage.

Prerequisites we lean on but never assume you remember: the one-transistor-one-capacitor cell, and why the chip needs refresh.

Step 0 — The only physics law we need

We measure "how much charge" a thing holds with three quantities:

Why this tool and not another? We are about to connect two charge-holders (a cell and a wire) and ask "what voltage results?". The only thing that is conserved in that connection is charge, and $Q = C V$ is the bridge between the charge we conserve and the voltage we can measure. That is exactly the question we have, so this is exactly the tool.

Figure — Row - column addressing and sense amplifiers

Step 1 — The two buckets, before anything happens

WHAT. We name our two charge-holders and their sizes. WHY. You cannot conserve charge until you know which containers hold it.

Step 2 — Fill each bucket to a known level (precharge + stored bit)

WHAT. We set the starting voltage of each capacitor. WHY. Charge-sharing gives a clean answer only if we know both starting levels.

Two setup moves happen before the read:

Meanwhile the cell has been holding its bit all along:

Why halfway and not full? Parking the tub at the midpoint means a full thimble will nudge it up and an empty thimble will nudge it down — a symmetric ± signal. If we parked at the top, an empty cell would cause a big drop and a full cell no change at all. (This is the "precharge to $V_{D D} /2$ " mistake in the parent note, seen as a picture.)

Step 3 — Open the tap: connect the buckets (turn on the wordline)

WHAT. Raising the wordline switches on the cell's access transistor, joining thimble and bathtub into one connected pool. WHY. This is the read event. The instant they connect, water levels start to equalize — and the physics of Step 0 takes over.

Now we apply "charge before = charge after". The charge just rearranges; the total is fixed.

Step 4 — Solve for the shared level $V_{final}$

WHAT. Rearrange the conservation equation to get the one number we can measure: the new bitline voltage. WHY. The sense amplifier reads the bitline, so $V_{final}$ is what it actually sees.

Divide both sides by $(C_{s} + C_{b})$ :

Step 5 — Subtract the reference to expose the signal $Δ V$

WHAT. We measure how far $V_{final}$ moved away from where it started ( $V_{D D} /2$ ). WHY. The sense amp compares the bitline against a reference sitting at $V_{D D} /2$ (its complement line $\overline{BL}$ ). Everything at $V_{D D} /2$ cancels; only the deviation carries the bit. Subtracting isolates exactly the part the cell caused.

Step 6 — Both cases: reading a 1 vs reading a 0

WHAT. Plug in the two possible cell voltages and watch the sign flip. WHY. The reader must never meet an unshown case. A cell is only ever a 1 or a 0 — here are both.

Notice the two magnitudes are identical — same size, opposite sign. That symmetry is the payoff of parking at $V_{D D} /2$ in Step 2.

Step 7 — The edge cases (never leave a scenario unshown)

WHAT. Push the formula to its limits and see what it predicts. WHY. The extremes reveal why the design choices are what they are — this is the mistake-proofing.

The one-picture summary

Everything above collapses into a single journey: two buckets of different size, poured together, and the tiny level-change that results — amplified into a solid bit.

Recall Feynman retelling — say it in plain words (click to reveal)

Every memory bit lives in a tiny bucket (the cell capacitor $C_{s}$ ). To read it, we first fill a huge bathtub (the long bitline wire $C_{b}$ ) exactly halfway. Then we open a tap between the tiny bucket and the tub. Water rushes to equalize — but the tub is so much bigger that the level barely moves: it ends up at a weighted average, only a hair above or below halfway. "A hair above" means the bucket was full (a 1); "a hair below" means it was empty (a 0). That hair is $Δ V = \frac{C _{s}}{C _{s} + C _{b}} (V_{cell} - \frac{V _{D D}}{2})$ — a fraction (the dilution) times how far the bucket started from the middle (the sign). It comes out as only tens of millivolts, so a sense amplifier grabs that faint nudge and yanks it to a full, confident 1 or 0. Two things can kill it: if the bucket ever drifts to the middle (a leak), the signal drops to zero and the bit is lost — that is why we refresh; and making the bucket bigger to boost the signal only helps up to a point, because the dilution fraction saturates at 1 while your chip balloons in size.

Recall

What does charge conservation say when cell and bitline connect? ::: Total charge before = total after: $C_{s} V_{cell} + C_{b} \frac{V _{D D}}{2} = (C_{s} + C_{b}) V_{final}$ . Why subtract $V_{D D} /2$ from $V_{final}$ ? ::: The reference line sits at $V_{D D} /2$ ; subtracting cancels everything common and leaves only the signal the cell caused. Why is $Δ V$ only tens of mV? ::: The dilution factor $\frac{C _{s}}{C _{s} + C _{b}}$ is tiny because $C_{b} ≫ C_{s}$ . What makes the signal symmetric for 0 and 1? ::: Precharging the bitline to the midpoint $V_{D D} /2$ , so a 1 gives $+ Δ V$ and a 0 gives an equal $- Δ V$ . What happens as a cell leaks toward $V_{D D} /2$ ? ::: $Δ V \to 0$ , the bit becomes unreadable — hence refresh.

Related: SRAM 6T cell (which avoids all of this by storing the bit in a self-holding latch), and CAS latency and memory timing (the clocks that gate when the sense amp fires).