Intuition The one-sentence ideaDRAM cells are slow and their speed barely improved over decades — so every generation of DDR is a trick to move more bits per clock edge off the same slow cells by making the interface wider, faster, and more clever, not by making the memory core faster.
Definition DRAM core vs. interfaceA DRAM chip has two very different parts:
The memory array (capacitor cells) — physically slow , limited by how fast a tiny capacitor charges/discharges. Its "column access time" has stayed near ~15 ns for ~25 years.
The I/O interface — the wires and buffers that ship bits to the CPU. This part has become dramatically faster.
WHY the split matters: you cannot make analog capacitors faster easily, so all evolution happens at the interface. The interface reads a big chunk from the slow array once , then streams it out fast.
Intuition The bucket-brigade pictureThink of the slow array as a well (slow to fill a bucket) and the interface as a conveyor belt (can run fast). You can't fill buckets faster, so instead you fill many buckets at once (wide prefetch ) and run the belt faster (higher I/O clock, both clock edges).
Definition SDRAM (Synchronous DRAM)Memory synchronized to a clock so the CPU and memory agree on exactly when data is valid. Data is transferred once per clock cycle — on the rising edge only. This is SDR = Single Data Rate.
If the bus clock is f c l k f_{clk} f c l k w w w
Intuition WHY DDR doubles speed "for free"A clock is a square wave: it goes up then down each cycle. SDR wastes the falling edge. DDR (Double Data Rate ) transfers data on both the rising and falling edge. Same clock, 2× the transfers — no faster core needed.
But there's a catch that drives the whole generation story:
Definition Prefetch bufferBecause the slow array can't feed data at the fast I/O edge rate, each read grabs n n n in parallel from the array (the prefetch ), then the interface streams those n n n prefetch width doubles each DDR generation so the fast bus never starves.
Gen
Prefetch (bits)
I/O clock ÷ core
Voltage
Typical data rate
SDR
1n
1×
3.3 V
100–166 MT/s
DDR
2n
1× (both edges)
2.5 V
200–400 MT/s
DDR2
4n
2×
1.8 V
400–1066 MT/s
DDR3
8n
4×
1.5 V
800–2133 MT/s
DDR4
8n (+ bank groups)
4×
1.2 V
1600–3200 MT/s
DDR5
16n (2× 8n subchannels)
—
1.1 V
3200–8400 MT/s
Intuition WHY prefetch stalls at 8n for DDR3→DDR4Doubling prefetch makes each access transfer a bigger fixed burst. Beyond 8n, the minimum burst becomes too large to be useful for CPUs (you'd fetch data you don't need — wasted bandwidth). So DDR4 kept prefetch at 8n but added bank groups (independent groups you can interleave), and DDR5 splits the channel into two independent 32-bit subchannels , each 8n prefetch → effectively 16n.
Worked example 1 — DDR3-1600 bandwidthGiven DDR3-1600, 64-bit channel. Find peak BW.
Why start with the name? "1600" is the data rate in MT/s already. That's transfers/sec = 1600 × 10 6 =1600\times10^6 = 1600 × 1 0 6 Why multiply by 8? 64 bits = 8 = 8 = 8 BW = 1600 × 10 6 × 8 = 12,800 MB/s = 12.8 GB/s \text{BW}=1600\times10^6 \times 8 = 12{,}800\ \text{MB/s} = 12.8\ \text{GB/s} BW = 1600 × 1 0 6 × 8 = 12 , 800 MB/s = 12.8 GB/s "PC3-12800" — the number is the GB/s ×1000.
Worked example 2 — Recover the core clock of DDR3-1600
Why divide by 2 first? DDR uses both edges → I/O clock = 1600 / 2 = 800 = 1600/2 = 800 = 1600/2 = 800 Why divide by 4 next? DDR3 prefetch is 8n and I/O clock is 4× core → core = 800 / 4 = 200 = 800/4 = 200 = 800/4 = 200 Punchline: the actual array still runs at ~200 MHz , exactly like old DDR — proof the core never sped up.
Worked example 3 — DDR5 vs DDR4 at equal frequencyCompare DDR4-3200 and DDR5-3200 (both 64-bit module, 3200 MT/s).
Why aren't they identical? Raw peak BW = 3200 × 8 = 25.6 =3200\times8=25.6 = 3200 × 8 = 25.6 Why is DDR5 still faster in practice? DDR5's module is two independent 32-bit subchannels . Two smaller independent accesses = better parallelism , fewer stalls waiting for one busy bank. Same peak, higher effective bandwidth.Why this step matters: it shows evolution is now about concurrency , not just clock.
Common mistake "DDR-400 means the RAM runs at 400 MHz."Why it feels right: the label literally says 400, and higher numbers are faster.
The truth: 400 is MT/s (mega-transfers/sec) , not MHz. The clock is 400 / 2 = 200 400/2=200 400/2 = 200 clock (MHz) or a data rate (MT/s)?"
Common mistake "DDR2 is faster because its memory cells are faster."Why it feels right: newer = faster, obviously the whole chip improved.
The truth: the core stayed ~200 MHz ; DDR2 doubled the prefetch (2n→4n) and ran the I/O clock at 2× core. Fix: separate core speed from interface speed .
Common mistake "More prefetch is always better, so DDR5 should be 32n."Why it feels right: each doubling doubled speed before.
The truth: huge prefetch = huge minimum burst , forcing you to read data you don't need → wasted bandwidth for real (random-ish) access patterns. That's why DDR4/5 used bank groups and subchannels instead. Fix: bandwidth ≠ useful bandwidth.
Recall Test yourself (hide the answers)
What single physical fact forces all the "interface trickery"? → the DRAM array's ~15 ns access time barely improves.
What does the "D" in DDR give you? → data on both clock edges = 2× transfers.
Prefetch of DDR3? → 8n.
Why did prefetch stop doubling after DDR3? → burst would get too large / wasteful; used bank groups & subchannels instead.
Convert DDR4-3200, 64-bit → GB/s? → 3200 × 8 / 1000 = 25.6 3200\times8/1000 = 25.6 3200 × 8/1000 = 25.6
Recall Feynman: explain to a 12-year-oldImagine a well with slow-to-fill water buckets (the memory) and a fast conveyor belt (the wires to the CPU). You can't fill buckets faster, so you fill lots of buckets at the same time and run the belt faster , and you put a bucket on the belt every time the belt-arm goes up AND down (that's the "double" in DDR). Each new DDR just fills more buckets at once and runs the belt faster — but the well itself never got faster. That's the whole secret.
Mnemonic Remember the doublings"Single Dares, Double, Double Double, Triple-Eight."
SDR=1n, DDR=2n, DDR2=4n, DDR3=8n (stays at 8 for DDR4), DDR5 splits into two → effective 16n.
And: "MT/s = MHz × 2" — data rate is always double the clock.
What is the key physical bottleneck driving DDR evolution? The DRAM array access time (~15 ns) barely improved, so speed gains come from the interface, not the core.
What does DDR (Double Data Rate) do? Transfers data on both the rising and falling clock edges, doubling transfers per clock cycle.
How is data rate (MT/s) related to bus clock (MHz)? Data rate = 2 × clock frequency (both edges).
What is the prefetch width for SDR, DDR, DDR2, DDR3? 1n, 2n, 4n, 8n respectively.
Why did prefetch stay at 8n from DDR3 to DDR4? Larger prefetch means larger minimum burst = wasted bandwidth; DDR4 used bank groups instead.
How does DDR5 effectively reach 16n prefetch? It splits each channel into two independent 32-bit subchannels, each with 8n prefetch.
Compute peak bandwidth of DDR4-3200 on a 64-bit channel. 3200 MT/s × 8 bytes = 25.6 GB/s.
What does "PC3-12800" mean? DDR3 module with 12800 MB/s peak bandwidth (= DDR3-1600).
What core clock does DDR3-1600 actually run at? 200 MHz (1600 ÷ 2 for edges ÷ 4 for 8n prefetch).
How did operating voltage evolve SDR→DDR5? 3.3 → 2.5 → 1.8 → 1.5 → 1.2 → 1.1 V (drops each generation to save power).
Why can DDR5 and DDR4 at the same MT/s differ in real performance? DDR5's dual subchannels give more parallelism/concurrency, reducing stalls despite equal peak bandwidth.
reads chunk once, streams fast
same slow core, faster IO
Intuition Hinglish mein samjhoDekho, DDR ki poori kahani ek simple fact pe tiki hai: DRAM ke andar jo capacitor cells hain, woh slow hain aur pichle 25 saal mein bilkul fast nahi hue — inka access time abhi bhi ~15 ns hai. Toh speed badhane ke liye engineers ne memory core ko touch hi nahi kiya, sirf interface (jo wires CPU tak data bhejti hain) ko tez banaya. Yehi asli trick hai.
Do main tricks hain. Pehla: DDR (Double Data Rate) — clock ek square wave hai jo upar-neeche jaata hai; SDR sirf rising edge pe data bhejta tha, DDR dono edges (rising + falling) pe bhejta hai, toh ek hi clock pe 2x transfers . Isliye "DDR-400" ka matlab clock 200 MHz hai, par data rate 400 MT/s (MT/s = MHz × 2, yaad rakhna). Dusra trick: prefetch — slow array se ek saath bahut saare bits parallel mein utha lo (SDR=1n, DDR=2n, DDR2=4n, DDR3=8n), phir fast bus pe stream kar do. Har generation prefetch double karti gayi.
DDR3 ke baad prefetch 8n pe ruk gaya. Kyun? Kyunki prefetch jitna bada, minimum burst utna bada — matlab tum aisa data bhi fetch kar loge jo chahiye hi nahi, bandwidth waste. Isliye DDR4 ne bank groups add kiye aur DDR5 ne channel ko do independent 32-bit subchannels mein tod diya (effective 16n), taaki parallelism badhe. Isliye DDR5 aur DDR4 same MT/s pe bhi, real life mein DDR5 tez lagta hai — kyunki concurrency zyada hai.
Bandwidth nikaalna easy hai: naam mein diya number hi MT/s hai, use bytes-per-transfer se multiply karo. Jaise DDR4-3200, 64-bit = 8 bytes → 3200 × 8 = 25600 MB/s = 25.6 GB/s. Aur voltage har generation mein girta gaya (3.3 → 1.1 V) taaki power aur heat bache. Bas yehi core intuition hai — baaki sab isi ke variations hain.
