Noesis
4.1.6 · D5Memory Technologies

Question bank — SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution

2,527 words11 min read↑ Back to topic

Before you attack the traps, let's build — from the picture up — the four ideas every question leans on: edges, prefetch, the master formula, and units. If any of these is fuzzy, the traps will fool you.

Build-up 1 — Why two edges = double the transfers

A clock is just a square wave: a voltage that steps up, holds, steps down, holds, and repeats. One full up-down-up is one cycle. Look at the figure: SDR (top) only samples data on the moment the wave goes up (the rising edge, blue dots). DDR (bottom) samples on both the up (blue) and the down (yellow) — same wave, twice the sampling moments.

Figure — SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution

Build-up 2 — What prefetch actually is (the pipeline picture)

The memory array (the grid of capacitor cells) is slow: one read takes ~15 ns to settle. The I/O bus (wires to the CPU) is fast. If we piped the array straight to the bus, the fast bus would sit idle waiting — starve — most of the time. The figure shows the fix: on one slow array read we grab a wide chunk of bits in parallel into a buffer, then a multiplexer streams them out one after another on the fast bus.

Figure — SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution

Build-up 3 — Deriving the master formula, one factor at a time

We want data rate = transfers per second off the pins. Build it as a chain, each factor answering "what multiplies the previous number, and why?"

Figure — SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution

Build-up 4 — Turning transfers into GB/s (the unit chain)

Names like "DDR3-1600" and "PC3-12800" hide a two-step unit conversion. Do it explicitly once and every bandwidth trap becomes obvious.

The figure lays these units end to end so you can watch MT/s + bytes/transfer collapse into GB/s, and shows where the ×2 lives (inside MT/s, not an extra multiply).

Figure — SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution

True or false — justify

True or false: "DDR-400 memory has an internal clock of 400 MHz."
False. 400 is the data rate in MT/s; the I/O clock is MHz, and the array core is slower still. The label counts transfers, not clock ticks.
True or false: "Each new DDR generation made the memory cells (the capacitors) respond faster."
False. The array's column-access time stayed near ~15 ns across all generations; every gain came from the interface (wider prefetch, faster I/O clock, more parallelism), not the core.
True or false: "DDR transfers twice as much data per clock cycle as SDR at the same clock frequency."
True. DDR uses both the rising and falling edge, so at identical clock it does 2 transfers per cycle versus SDR's 1 — this is the "free" doubling that costs no faster core.
True or false: "A DDR4-3200 and a DDR5-3200 module have exactly the same peak bandwidth."
True for peak — both are GB/s on a 64-bit module. But DDR5 splits into two independent 32-bit subchannels, so its effective/useful bandwidth is higher due to concurrency.
True or false: "Because prefetch doubled every generation from SDR to DDR3, DDR5 must use 32n prefetch."
False. Prefetch stopped doubling at 8n (DDR3/DDR4) because a bigger minimum burst forces reading data you don't need. DDR5 instead runs two 8n subchannels for an effective 16n.
True or false: "Higher voltage each generation is what makes DDR faster."
False — it's the opposite. Voltage dropped each gen (3.3 → 2.5 → 1.8 → 1.5 → 1.2 → 1.1 V) to cut power and heat as speeds rose. See Signal integrity and voltage scaling.
True or false: "MT/s and MHz are just two names for the same number."
False. MHz is a clock rate (edges of a square wave per second); MT/s is a transfer rate (data words per second). For DDR, because of the double edges (see Build-up 1).
True or false: "Doubling the bandwidth number halves the latency."
False. Bandwidth is how many bytes per second; latency is how long one access takes. They are almost independent — the ~15 ns first-access delay barely moved. See Memory bandwidth vs latency.

Spot the error

Find the flaw: "DDR3-1600 runs its array at 1600 MHz, so it's 8× faster than 200 MHz DDR."
The array does not run at 1600 MHz. Divide by 2 (edges) → 800 MHz I/O clock, then by 4 (prefetch 8n over I/O) → 200 MHz core, same as old DDR. The "1600" is data rate, and the core never sped up.
Find the flaw: "To get bandwidth, multiply the clock in MHz by the byte width."
You must use the data rate (MT/s), not the clock. For DDR that's the clock, so multiplying the raw clock undercounts by a factor of 2 (see the unit chain, Build-up 4).
Find the flaw: "Prefetch is a cache inside the memory that stores recently used data."
No — prefetch is not a cache and holds nothing "recent." It is the fixed number of bits grabbed in parallel from the array on every single access, then streamed out fast so the bus never starves. It has no reuse logic.
Find the flaw: "Bank groups let DDR4 fetch more bits per access than DDR3."
Both are 8n prefetch — same bits per access. Bank groups instead let different accesses overlap in time (interleave), hiding array delay, not enlarging the burst.
Find the flaw: "DDR5's two subchannels double the peak bandwidth over a same-rated DDR4."
Peak is set by (data rate × total width) and is the same at equal rate and width. The subchannels raise useful bandwidth via parallelism; they do not change the peak number.
Find the flaw: "PC3-12800 means the module runs at 12800 MHz."
The "12800" is MB/s of bandwidth (), not a clock. The naming ties the module label to GB/s×1000, not frequency.
Find the flaw: "SDR was replaced because engineers found a way to charge capacitors faster."
Capacitor charge time is a physical limit that was not overcome. SDR was replaced by exploiting the idle falling edge and prefetching wider — pure interface tricks.

Why questions

Why can't we just keep raising the DRAM core clock instead of all this prefetch/edge trickery?
The core is limited by how fast a tiny analog capacitor charges/discharges (~15 ns), which is physics, not engineering choice. So designers work around it at the interface. See DRAM cell structure and refresh.
Why does the prefetch buffer exist at all — why not read straight from the array to the bus?
The array is far slower than the I/O bus. Grabbing bits in parallel once, then streaming them out fast, lets the quick bus stay busy while the slow array recovers — otherwise the fast bus would starve (Build-up 2).
Why did prefetch stop doubling after 8n?
Each doubling doubles the minimum burst length. Past 8n the forced burst is larger than typical CPU requests, so you fetch bytes you throw away — wasted bandwidth on realistic access patterns.
Why does DDR5 split a channel into two 32-bit subchannels instead of just widening prefetch?
Two independent narrower accesses give concurrency: while one subchannel waits on a busy bank, the other still transfers. This raises useful bandwidth without inflating the burst size.
Why does voltage drop with each generation even as speed rises?
Higher switching speed means more power and heat; lowering voltage keeps power in check and eases signal integrity at high rates. See Signal integrity and voltage scaling.
Why is DDR evolution now described as "about concurrency, not clock"?
The core clock is frozen and prefetch hit its useful ceiling, so the remaining lever is overlapping many independent accesses (bank groups, subchannels) to hide the fixed array delay.
Why does the "15 ns" number keep appearing in timing discussions?
It's the array's column-access time — the physical delay that CAS latency counts out in clock cycles. As clocks get faster, the same 15 ns spans more cycles, so CL numbers rise. See CAS latency and memory timings.

Edge cases

Edge case: if you clock DDR memory but only ever use the rising edge, what have you built?
Effectively SDR — one transfer per cycle. The "double" in DDR is exactly the falling-edge transfer; drop it and you're back to single data rate.
Edge case: at prefetch = 1n and 1 edge per cycle, what generation does the formula collapse to?
SDR SDRAM — the degenerate baseline: , one transfer per clock, no doubling and no wide prefetch.
Edge case: two modules have the same MT/s but one is DDR4 and one DDR5 — which wins on a purely sequential, one-request-at-a-time workload?
Roughly a tie. DDR5's advantage is concurrency; with zero overlapping requests there's little parallelism to exploit, so effective bandwidth converges toward the identical peak.
Edge case: what happens to peak bandwidth if the bus width is halved but the data rate stays fixed?
Peak bandwidth halves — it is (transfers/sec) × (bytes/transfer), and you cut the bytes per transfer in half. This is exactly why each DDR5 subchannel (32-bit) alone has half a full channel's peak.
Edge case: a workload does tiny, scattered random reads — does a very large prefetch help or hurt?
It hurts. Each access drags in a big burst mostly discarded, so real useful throughput drops even though peak bandwidth looks high — the "bandwidth ≠ useful bandwidth" trap.
Edge case: at a data rate of essentially 0 MT/s (idle bus), what is the array core doing?
Still consuming its ~15 ns access floor per access and periodically refreshing its capacitors regardless of transfer activity — the core's limits don't vanish just because the interface is quiet.

Connections