Foundations — SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution

This page assumes nothing. If you have never seen "MHz", "64-bit bus", "ns", or "$\times 10^6$", start here and read top to bottom. Every symbol used in the parent topic is built below, in the order you need them.

1. A bit, a byte, and a bus width $w$

Why the topic needs $w$: bandwidth is "how many bytes per second". Wider bus = more bytes per single transfer. To turn bits into bytes we divide by 8, which is why you will always see $\frac{w}{8}$ in the formulas.

2. Time, seconds, and the nanosecond (ns)

Why the topic needs ns: the parent note keeps quoting "the array access time is ~15 ns". That is the time the slow charge-buckets take to hand over their data. Holding this number lets you see how slow the core really is compared to the interface.

3. Frequency, Hertz, and the clock $f_{clk}$

A clock is a square wave — it rises to "high", stays, falls to "low", stays, and repeats. This shape has two special moments per cycle: the rising edge (going up) and the falling edge (going down). Remember these two edges — the entire DDR ("Double Data Rate") trick lives on them.

4. Scientific notation: reading $\times 10^6$

Why the topic needs it: every bandwidth number is millions or billions. When the parent writes $100\times 10^6\times 8=800$ MB/s, it is just (100 million transfers) × (8 bytes each) = 800 million bytes per second.

5. Transfers per second, and MT/s

Why the topic splits "clock" from "transfers": for old SDR memory there is exactly one transfer per clock cycle, so transfers/sec $=f_{clk}$. But DDR fires on both edges, giving two transfers per cycle. So transfers/sec $=2\times f_{clk}$. The label "DDR-400" is 400 MT/s, meaning the clock is only $400/2=200$ MHz.

6. The slow core vs the fast interface, and "prefetch $n$"

Why the topic needs $n$: the master relationship of the whole page is $f_{\text{I/O data rate}}=\underset{\approx \text{constant}}{\underbrace{f_{\text{core}}}}\times \text{prefetch}.$ The core clock stays put; the prefetch and I/O clock multiply the data rate up.

Prerequisite map

Read it as: bits and clocks at the top feed into transfers and bandwidth; the slow-array fact feeds the prefetch idea; together they explain the DDR evolution in the parent topic.

Equipment checklist

Test yourself — hide the right side and answer each.

Connections

• DRAM cell structure and refresh — the slow capacitor bucket behind the ~15 ns
• Memory bandwidth vs latency — bandwidth (built here) vs delay
• CAS latency and memory timings — where the 15 ns turns into clock counts
• Bank groups and interleaving — the next trick after prefetch stalls
• Cache and the memory hierarchy — who consumes the bandwidth
• Signal integrity and voltage scaling — why faster wires need lower voltage