Exercises — SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution

(a) The name is the data rate. So $3200$ MT/s. WHY: by convention the number after "DDR-" is always MT/s, never MHz. (b) Undo the double-edge trick — divide by $2$: $f_{\text{I/O}}=\frac{3200}{2}=1600\text{ MHz}$ What it looks like: one full clock tick = one up-edge + one down-edge = two transfers. So the ticks (1600 M of them) are half the transfers (3200 M).

• SDR $=1n$
• DDR $=2n$
• DDR2 $=4n$
• DDR3 $=8n$

WHY the doubling: each generation grabs twice as many bits in parallel from the slow array per read, so the faster interface never runs out of bits to stream. The mnemonic: "Single, Double, Double-Double, Triple-Eight."

• "PC3" $\Rightarrow$ DDR3.
• "12800" is the peak bandwidth in MB/s $=12.8$ GB/s. WHY two names for one stick? "DDR3-1600" names the transfers (1600 MT/s); "PC3-12800" names the bandwidth (1600 × 8 bytes = 12800 MB/s). They describe the same stick from two angles.

• transfers/sec $=1600\times 10^6$ (the name is the data rate).
• bytes per transfer $=64/8=8$. $\text{BW}=1600\times 10^6\times 8=12,800\text{ MB/s}=12.8\text{ GB/s}$ WHY divide by 8: the bus carries $64$ bits at once, but bandwidth is quoted in bytes, and $8$ bits $=1$ byte.

$\text{BW}=6400\times 10^6\times \frac{64}{8}=6400\times 10^6\times 8=51,200\text{ MB/s}=51.2\text{ GB/s}$ WHY the same formula works: peak bandwidth only cares about how many transfers and how wide. The subchannel split inside DDR5 does not change the peak — it changes the effective rate (see L3.2).

$\text{BW}=2400\times 10^6\times \frac{8}{8}=2400\times 10^6\times 1=2400\text{ MB/s}=2.4\text{ GB/s}$ WHY this matters: a 64-bit module is built from eight x8 chips side by side. $8\times 2.4=19.2$ GB/s — matching a full 64-bit DDR4-2400 module. See the figure below.

DDR3-1600:

• Undo double-edge: $1600/2=800$ MHz I/O clock.
• DDR3 I/O runs at $4\times$ core (prefetch $8n$): $800/4=200$ MHz core.

DDR-400:

• Undo double-edge: $400/2=200$ MHz I/O clock.
• DDR I/O runs at $1\times$ core (prefetch $2n$): $200/1=200$ MHz core.

Both cores $=200$ MHz. This is the punchline of the whole topic: the slow capacitor array (~15 ns, see DRAM cell structure and refresh) never sped up. Every gain lives in the interface.

Peak (identical): $\text{BW}=3200\times 10^6\times 8=25.6\text{ GB/s (both)}$ Why DDR5 still wins: the DDR4 module is one $64$-bit channel — one access at a time uses the whole width. The DDR5 module is two independent 32-bit subchannels. Two smaller, independent requests can be in flight at once, so while one subchannel waits on a busy bank the other keeps delivering. Same peak, higher effective bandwidth. This is Bank groups and interleaving taken to the channel level. What it looks like: one wide lane vs. two narrower lanes — same total width of asphalt, but two cars can move independently instead of queuing behind one.

• Bytes per burst $=8\text{ transfers}\times 8\text{ bytes}=64$ bytes. WHY it is fixed at 8: the prefetch is $8n$ — the array hands the interface $8$ chunks in parallel at once, so the interface is committed to streaming all $8$ out. You physically cannot stop after $4$. Why 64 bytes is convenient: that is exactly one CPU cache line (see Cache and the memory hierarchy). The burst was designed to fill one cache line per read — no waste.

(a) Reverse the bandwidth formula: $\text{MT/s}=\frac{\text{BW}}{w/8}=\frac{21,333\text{ MB/s}}{8}\approx 2667\text{ MT/s}$ (b) $2667$ MT/s falls in the DDR4 range (1600–3200). It is DDR4-2666 (a very common speed). Its label would read PC4-21300. WHY work backwards: the same three tools run in either direction — bandwidth ↔ transfers ↔ clock are all one chain of multiplications you can invert.

(a) Each subchannel still runs at the full data rate $6400$ MT/s (the split is in width, not speed), but is only $32$ bits wide: ${\text{BW}}_{\text{sub}}=6400\times 10^6\times \frac{32}{8}=6400\times 10^6\times 4=25.6\text{ GB/s}$ (b) Two subchannels: $25.6\times 2=51.2$ GB/s — exactly the L2.2 module peak. ✓ WHY it adds up: splitting $64$ bits into $2\times 32$ bits keeps the total width $64$, so total peak is unchanged; the win is that the two halves are independent (concurrency, not raw peak).

• $16$ transfers $\times 8$ bytes $=128$ bytes per forced burst.
• A CPU cache line is $64$ bytes. A $128$-byte forced burst means every read drags in a second cache line you may not need — half the bandwidth can be wasted on random-access patterns. This is exactly why prefetch stopped at 8n. Instead of bigger bursts, DDR4 added bank groups and DDR5 added subchannels — both increase parallelism without inflating the minimum burst. See Bank groups and interleaving.

(a) A $15$ ns access ≈ one core cycle, so period $\approx 15$ ns $\Rightarrow$ $f_{\text{core}}=\frac{1}{15\times 10^{-9}}\approx 66.7\text{ MHz}$ (Real cores pipeline sub-operations to reach ~200 MHz; $15$ ns is the full column-access latency, not one pipeline stage — that is why measured core clocks sit near $200$ MHz while access latency stays ~$15$ ns.) (b) At $4\times$ core (using ~$200$ MHz effective core): I/O $=800$ MHz, data rate $=1600$ MT/s — a plausible DDR4 low bin. (c) The $15$ ns limits latency (how long until the first byte arrives), not bandwidth. Bandwidth is fixed by the streaming interface once data starts flowing. This is the core message of Memory bandwidth vs latency and CAS latency and memory timings: prefetch and DDR raise bandwidth, but first-access latency has barely moved in decades.

• B (two DDR4 channels) wins when many independent threads each issue small random requests: two fully independent physical channels means two requests truly proceed at once with separate command buses — maximum concurrency, hiding the ~15 ns latency of one busy bank.
• A (one fast DDR5 channel) wins on long sequential streaming from few threads: the higher raw MT/s streams a big contiguous block faster, and DDR5's built-in two subchannels already give it modest concurrency. WHY this is "mastery": peak bandwidth (a single number) hides the real question — how many independent requests can be in flight? Modern DDR evolution optimizes concurrency, not just the peak. That is the whole L3→L5 arc of this topic.

• DDR4-3200 clock? ::: 1600 MHz (data rate ÷ 2).
• DDR3-1600, 64-bit BW? ::: 12.8 GB/s.
• DDR5-6400, 64-bit BW? ::: 51.2 GB/s.
• Core clock of DDR3-1600? ::: ~200 MHz (÷2 then ÷4).
• Bytes in a DDR3 BL8 burst (64-bit)? ::: 64 bytes = one cache line.
• Why did prefetch freeze at 8n? ::: bigger bursts waste bandwidth; use bank groups & subchannels instead.
• Two 32-bit DDR5 subchannels at 6400 → total? ::: 51.2 GB/s (2 × 25.6).