SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution: Worked examples

Definition Terms used on this page

I/O clock — see above; the tick-rate of the wires shipping bits to the CPU.
prefetch multiplier — the whole-number ratio $\frac{f _{I/O}}{f _{core}}$ , i.e. how many times faster the wires tick than the core. For SDR/DDR it is $1$ , DDR2 it is $2$ , DDR3/DDR4 it is $4$ . (It rises because a wider prefetch lets the wires run proportionally faster without starving.) We will write it as $m = f_{I/O} / f_{core}$ , so the master relationship is $f_{I/O} = f_{core} \times m$ .
burst — a fixed, unbreakable run of transfers produced by one read. Because one prefetch grabs many bits at once, they must all be streamed out together; you cannot ask for "just half a burst." Burst length is measured in transfers, or (times bytes-per-transfer) in bytes.
bank group — an independent sub-section of the array (introduced in DDR4) you can access in parallel with another; more in Bank groups and interleaving.
byte convention on this page: we use decimal units throughout — $1 MB = 1 0^{6}$ bytes and $1 GB = 1000 MB = 1 0^{9}$ bytes. This is the convention memory-module marketing (the "PCx-" labels) uses, so GB/s ×1000 always matches the printed number.

The scenario matrix

Every problem this topic throws at you is one of these cells. The worked examples below are labelled with the cell they cover.

#	Case class	What makes it tricky	Covered by
A	Name → bandwidth (forward)	remembering "the number is MT/s"	Ex 1
B	Bandwidth → name (reverse)	dividing back out, matching the "PCx-" label	Ex 2
C	Recover the core clock	two divisions (edges, then prefetch multiplier $m$ )	Ex 3
D	Degenerate: SDR (prefetch 1n, one edge)	the formula with all multipliers = 1	Ex 4
E	Cross-generation, equal MT/s	equal peak, different effective BW	Ex 5
F	Multi-channel / real-world word problem	channels multiply, don't change per-channel maths	Ex 6
G	Unit trap / exam twist (MHz vs MT/s mislabel)	spotting the wrong unit before computing	Ex 7
H	Limiting case: "why not 32n prefetch?"	minimum burst grows, useful BW falls	Ex 8

Example 1 — Name → bandwidth (Cell A)

Example 2 — Bandwidth → name (Cell B)

Example 3 — Recover the core clock (Cell C)

Worked example DDR4-3200 again. What is the slow

array (core) clock $f_{core}$ ? Forecast: 3200 MHz, 800 MHz, or 200 MHz?

Figure s01: a left-to-right chain of three rounded boxes. The coral box "3200 MT/s (the stamped name)" flows through a lavender arrow labelled "÷2 (both edges)" into the butter box "1600 MHz I/O clock

f_{I/O}

", then through a second lavender arrow labelled "÷4 (prefetch multiplier

m

)" into the mint box "400 MHz core clock

f_{core}

". Below, a white callout rebuilds forward:

400 \times 4 \times 2 = 3200

MT/s. Read the two arrows as the two undo-operations of this example.

Step 1 — Undo the "double edge": divide by 2. Why this step? DDR sends 2 transfers per clock tick (rising + falling edge). To get back to ticks per second (the I/O clock $f_{I/O}$ , defined in the Symbols box) we halve the transfers. This is the first arrow in figure s01. $f_{I/O} = \frac{3200}{2} = 1600 MHz$

Step 2 — Undo the prefetch multiplier $m$ : divide by 4. Why this step? From the Terms box, $f_{I/O} = f_{core} \times m$ where $m = f_{I/O} / f_{core}$ is the prefetch multiplier. For DDR4, $m = 4$ (the wires tick 4× faster than the core). This is the second arrow in figure s01. So we recover the core by dividing by $m$ : $f_{core} = \frac{f _{I/O}}{m} = \frac{1600}{4} = 400 MHz$

Verify: rebuild forward — $f_{core} \times m \times 2 = 400 \times 4 \times 2 = 3200$ MT/s ✓. Notice: even at DDR4-3200 the actual capacitors run at only 400 MHz — the whole point of the parent note.

Example 4 — Degenerate case: SDR (Cell D)

Worked example "PC100" SDR SDRAM, 64-bit, clock 100 MHz. Find BW and confirm every DDR multiplier collapses to 1.

Forecast: should be lower than any DDR — around 0.8 GB/s.

Step 1 — Transfers/sec with all multipliers = 1. Why this step? SDR uses one edge (×1, not ×2) and 1n prefetch so its multiplier $m = 1$ . So transfers/sec $= f_{c l k} = 100 \times 1 0^{6}$ . This is the boundary the whole family builds up from.

Step 2 — Bytes per transfer $= 64/8 = 8$ . Why this step? Same bus-width→bytes conversion as always; nothing about the bus width changed.

Step 3 — Multiply. $BW = 100 \times 1 0^{6} \times 8 = 800 MB/s = 0.8 GB/s$

Verify: SDR modules are named two ways — a frequency label ("PC100", from the 100 MHz clock) and, if a bandwidth label existed, it would read the MB/s figure. Here the bandwidth is 800 MB/s. (Do not confuse this with "PC-6400", which is the DDR2-800 bandwidth label — a different generation entirely; the SDR PC-numbers are clock-based, the later PCx- numbers are bandwidth-based.) Sanity: this matches the parent note's SDR example, and it is 32× slower than DDR4-3200 ( $25.6$ GB/s ÷ $0.8$ = 32) ✓.

Example 5 — Equal MT/s, different generation (Cell E)

Worked example DDR4-3200 vs DDR5-3200, both 64-bit modules. Compare

peak and effective bandwidth — with numbers. Forecast: identical peak? Or is DDR5 higher on paper?

Figure s02: two labelled stacks. On the left, "DDR4-3200" shows one wide lavender box "one 64-bit channel" feeding a single butter box "1 access stream", tagged "peak 25.6 GB/s". On the right, "DDR5-3200" shows two mint boxes "32-bit sub A" and "32-bit sub B" each feeding its own coral "stream A" / "stream B" box, tagged "peak 25.6 GB/s, 2 streams". The two layouts have the same total width (same peak) but the right one has two independent columns (the concurrency that raises effective BW).

Step 1 — Peak BW of each. Why this step? Peak only depends on MT/s × bytes: both are $3200 \times 8 = 25, 600$ MB/s $= 25.6$ GB/s. Peaks are equal — as the equal total width in figure s02 shows.

Step 2 — Model a stall to make "effective" concrete. Why this step? "Effective" BW = peak × the fraction of time the bus is actually delivering data (its utilisation). Suppose a workload keeps each access busy 75% of the time and idle (waiting on a busy bank) 25% of the time.

DDR4 (one 64-bit stream): when that single stream stalls, nothing flows. Utilisation $= 75% = 0.75$ . $effective_{DDR4} = 0.75 \times 25.6 = 19.2 GB/s$

Step 3 — Two independent subchannels overlap their stalls. Why this step? With two 32-bit streams (figure s02, right), the two stalls are independent. The bus is fully idle only when both stall at once: probability $0.25 \times 0.25 = 0.0625$ . So combined utilisation $= 1 - 0.0625 = 0.9375$ . $effective_{DDR5} = 0.9375 \times 25.6 = 24.0 GB/s$

Verify: peaks equal — $3200 \times 8 = 25, 600$ MB/s for both ✓. Under this simple independence model, effective jumps from $19.2$ to $24.0$ GB/s — a $+ 25%$ gain from concurrency alone, with no change in peak. The real mechanism (independent bank groups per subchannel) is more detailed, but the direction and magnitude are exactly this: peak equal, effective DDR5 > DDR4.

Example 6 — Real-world word problem: dual channel (Cell F)

Example 7 — Unit trap / exam twist (Cell G)

Example 8 — Limiting case: why prefetch stops at 8n (Cell H)

Worked example Suppose engineers pushed prefetch to

32n on a 64-bit channel. Show why the minimum burst becomes the problem. Forecast: how many bytes must you fetch even if the CPU wants just 8?

Figure s03: a small mint reference box "64 B cache line" at top, then three horizontal bars whose lengths are proportional to burst size: an 8n mint bar labelled "8n = 64 B", a 16n butter bar "16n = 128 B", and a 32n coral bar "32n = 256 B" — visibly four times the cache-line box. A white callout at the bottom reads "CPU wants 64 B → 32n forces 256 B → useful = 64/256 = 25%". The bars are the bursts; longer bar = more forced, unused data.

Step 1 — Write the minimum-burst formula and read each factor. Why this step? A burst (Terms box) is the unbreakable run of transfers from one prefetch. One prefetch of $n$ produces $n$ transfers, and each transfer on a 64-bit bus carries $64/8 = 8$ bytes. So: $min burst (bytes) = transfers per burst n \times bytes per transfer \frac{bus width in bits}{8} = n \times \frac{64}{8} = n \times 8$ (Here "bus width in bits / 8" is the bytes per transfer; nothing more mysterious than Example 1's "8 bytes.")

prefetch $n$	min burst $= n \times 8$ (bytes)
8n	$8 \times 8 = 64$
16n	$16 \times 8 = 128$
32n	$32 \times 8 = 256$

Step 2 — Compare to a CPU cache line (64 bytes). Why this step? CPUs move memory in 64-byte cache lines. In figure s03, the 8n bar matches the cache-line box exactly; a 32n bar is 256 bytes — 4× a cache line.

Step 3 — Useful-bandwidth loss. Why this step? If the workload needs only 64 bytes but you must read 256, you waste 192 bytes. Useful fraction $= 64/256 = 25%$ . That's why DDR4/5 kept 8n and added bank groups and subchannels instead of enlarging the burst.

Verify: $32 \times 8 = 256$ bytes ✓; wasted $= 256 - 64 = 192$ bytes; useful fraction $64/256 = 0.25 = 25%$ ✓. Bandwidth ≠ useful bandwidth — the parent note's third mistake, now with numbers.

Active recall

Recall Cover the answers

DDR4-3200, 64-bit → GB/s? → $3200 \times 8/1000 = 25.6$ GB/s.
21.3 GB/s, 64-bit → which grade? → $21300/8 \approx 2666$ → DDR4-2666.
Core clock of DDR4-3200? → $3200/2/4 = 400$ MHz (÷2 edges, ÷ $m = 4$ ).
Two DDR5-6400 channels total BW? → $2 \times 6400 \times 8 = 102.4$ GB/s.
"800 MHz DDR3" true data rate? → $2 \times 800 = 1600$ MT/s (DDR3-1600).
32n prefetch min burst on 64-bit bus? → 256 bytes; only 25% useful vs a 64-byte line.

Connections

Parent topic (Hinglish)
Memory bandwidth vs latency — Example 5's "peak vs effective" made precise
Bank groups and interleaving — why concurrency beats bigger bursts
Cache and the memory hierarchy — the 64-byte cache line in Example 8
CAS latency and memory timings — more MHz-vs-MT/s unit traps
Signal integrity and voltage scaling — the cost of pushing MT/s higher
DRAM cell structure and refresh — the 400 MHz core that never sped up

DDR4-3200 on a 64-bit channel, peak bandwidth?

3200 × 8 = 25.6 GB/s (PC4-25600).

Core clock of DDR4-3200?

3200 ÷ 2 (edges) ÷ 4 (prefetch multiplier m) = 400 MHz.

Why not use 32n prefetch?

Minimum burst becomes 256 bytes vs a 64-byte cache line — only 25% useful, so DDR4/5 use bank groups and subchannels instead.