4.1.6
Intuition Ek-sentence ideaDRAM cells slow hain aur unki speed decades mein barely improve hui hai — isliye DDR ki har generation ek trick hai jisse zyada bits per clock edge usi slow cells se move kiye jaate hain — interface ko wider, faster, aur more clever banakar, na ki memory core ko faster banakar.
Definition DRAM core vs. interfaceEk DRAM chip ke do bahut alag parts hote hain:
Memory array (capacitor cells) — physically slow , limited by ye ki ek tiny capacitor kitni fast charge/discharge ho sakta hai. Iska "column access time" ~25 saalon se ~15 ns ke paas hi raha hai.I/O interface — wires aur buffers jo bits ko CPU tak pohonchaate hain. Ye part dramatically faster ho gaya hai.
WHY the split matters: analog capacitors ko asaani se faster nahi banaya ja sakta, isliye saari evolution interface par hoti hai. Interface slow array se ek baar mein ek bada chunk padhta hai, phir usse fast stream out karta hai.
Intuition Bucket-brigade pictureSocho slow array ek well hai (ek bucket fill karna slow hai) aur interface ek conveyor belt hai (fast chal sakti hai). Tum buckets faster fill nahi kar sakte, isliye ek saath bahut saare buckets fill karte ho (wide prefetch ) aur belt faster chalate ho (higher I/O clock, both clock edges).
Definition SDRAM (Synchronous DRAM)Memory clock ke saath synchronized hoti hai taki CPU aur memory exactly agree kar sakein ki data kab valid hai. Data ek clock cycle mein ek baar transfer hota hai — sirf rising edge par. Ye hai SDR = Single Data Rate.
Agar bus clock f c l k w
Intuition WHY DDR "for free" double speed karta haiEk clock ek square wave hai: ye har cycle mein upar phir neeche jaata hai. SDR falling edge waste karta hai. DDR (Double Data Rate ) dono rising aur falling edge par data transfer karta hai. Same clock, 2× transfers — koi faster core ki zaroorat nahi.
Lekin ek catch hai jo poori generation story ko drive karti hai:
Definition Prefetch bufferKyunki slow array fast I/O edge rate par data feed nahi kar sakta, har read array se n parallel mein grab karta hai (prefetch ), phir interface un n Prefetch width har DDR generation mein double hoti hai taki fast bus kabhi starve na ho.
Gen
Prefetch (bits)
I/O clock ÷ core
Voltage
Typical data rate
SDR
1n
1×
3.3 V
100–166 MT/s
DDR
2n
1× (both edges)
2.5 V
200–400 MT/s
DDR2
4n
2×
1.8 V
400–1066 MT/s
DDR3
8n
4×
1.5 V
800–2133 MT/s
DDR4
8n (+ bank groups)
4×
1.2 V
1600–3200 MT/s
DDR5
16n (2× 8n subchannels)
—
1.1 V
3200–8400 MT/s
Intuition WHY prefetch DDR3→DDR4 par 8n par stall ho gayiPrefetch double karne se har access ek bada fixed burst transfer karta hai. 8n ke baad, minimum burst itna bada ho jaata hai ki CPU ke liye useful nahi rehta (tum woh data fetch karte ho jo chahiye nahi — wasted bandwidth). Isliye DDR4 ne prefetch 8n par rakhi lekin bank groups add kiye (independent groups jo tum interleave kar sako), aur DDR5 channel ko do independent 32-bit subchannels mein split karta hai, har ek 8n prefetch → effectively 16n.
Worked example 1 — DDR3-1600 bandwidthGiven DDR3-1600, 64-bit channel. Peak BW nikalo.
Naam se kyon shuru karein? "1600" already data rate in MT/s hai. Matlab transfers/sec = 1600 × 1 0 6 8 se multiply kyon karein? 64 bits = 8 BW = 1600 × 1 0 6 × 8 = 12 , 800 MB/s = 12.8 GB/s "PC3-12800" stamp hota hai — number hai GB/s ×1000.
Worked example 2 — DDR3-1600 ka core clock recover karo
Pehle 2 se kyon divide karein? DDR dono edges use karta hai → I/O clock = 1600/2 = 800 Phir 4 se kyon divide karein? DDR3 prefetch 8n hai aur I/O clock, core ka 4× hai → core = 800/4 = 200 Punchline: actual array abhi bhi ~200 MHz par run karta hai, bilkul purane DDR ki tarah — proof ki core kabhi fast nahi hua.
Worked example 3 — Equal frequency par DDR5 vs DDR4DDR4-3200 aur DDR5-3200 compare karo (dono 64-bit module, 3200 MT/s).
Ye identical kyon nahi hain? Raw peak BW = 3200 × 8 = 25.6 DDR5 practice mein phir bhi faster kyon hai? DDR5 ka module do independent 32-bit subchannels hai. Do chhote independent accesses = better parallelism , ek busy bank ka wait karte hue kam stalls. Same peak, higher effective bandwidth.Ye step kyon matter karta hai: ye dikhata hai ki evolution ab concurrency ke baare mein hai, sirf clock ke baare mein nahi.
Common mistake "DDR-400 ka matlab hai RAM 400 MHz par run karti hai."Kyun sahi lagta hai: label literally 400 kehta hai, aur bade numbers hain faster.
Sach: 400 MT/s (mega-transfers/sec) hai, MHz nahi. Clock hai 400/2 = 200 clock (MHz) hai ya ek data rate (MT/s)?"
Common mistake "DDR2 faster hai kyunki uske memory cells faster hain."Kyun sahi lagta hai: newer = faster, obviously poori chip improve hui.
Sach: core ~200 MHz par raha ; DDR2 ne prefetch double ki (2n→4n) aur I/O clock ko core ke 2× par run kiya. Fix: core speed ko interface speed se alag karo.
Common mistake "Zyada prefetch hamesha better hai, isliye DDR5 ko 32n hona chahiye."Kyun sahi lagta hai: har doubling ne pehle speed double ki thi.
Sach: bada prefetch = bada minimum burst , jo tumhe woh data padhne par majboor karta hai jo tumhe chahiye nahi → real (random-ish) access patterns ke liye wasted bandwidth. Isliye DDR4/5 ne bank groups aur subchannels use kiye. Fix: bandwidth ≠ useful bandwidth.
Recall Khud test karo (answers hide karo)
Woh ek physical fact kya hai jo saari "interface trickery" force karta hai? → DRAM array ka ~15 ns access time barely improve hota hai.
DDR mein "D" tumhe kya deta hai? → Dono clock edges par data = 2× transfers.
DDR3 ka prefetch? → 8n.
Prefetch DDR3 ke baad doubling kyon ruk gayi? → Burst bahut bada / wasteful ho jaata; bank groups & subchannels use kiye.
DDR4-3200, 64-bit ko GB/s mein convert karo? → 3200 × 8/1000 = 25.6
Recall Feynman: 12-saal ke bachchey ko samjhaoSocho ek well hai jismein slow-fill hone wale paani ke buckets hain (memory) aur ek fast conveyor belt hai (CPU tak wires). Tum buckets faster fill nahi kar sakte, isliye tum ek saath bahut saare buckets fill karte ho aur belt faster chalate ho, aur tum belt par ek bucket tab rakhte ho jab belt-arm upar aur neeche dono baar jaata hai (wahi hai DDR mein "double"). Har naya DDR bas ek saath zyada buckets fill karta hai aur belt faster chalata hai — lekin well khud kabhi faster nahi hui. Ye hai poora secret.
Mnemonic Doublings yaad rakho"Single Dares, Double, Double Double, Triple-Eight."
SDR=1n, DDR=2n, DDR2=4n, DDR3=8n (DDR4 ke liye 8 par rukta hai), DDR5 do mein split ho jaata hai → effective 16n.
Aur: "MT/s = MHz × 2" — data rate hamesha clock ki double hoti hai.
DDR evolution ko drive karne wala key physical bottleneck kya hai? DRAM array access time (~15 ns) barely improve hua, isliye speed gains interface se aate hain, core se nahi.
DDR (Double Data Rate) kya karta hai? Dono rising aur falling clock edges par data transfer karta hai, clock cycle per transfers double karta hai.
Data rate (MT/s) bus clock (MHz) se kaise related hai? Data rate = 2 × clock frequency (dono edges).
SDR, DDR, DDR2, DDR3 ka prefetch width kya hai? Krama se 1n, 2n, 4n, 8n.
DDR3 se DDR4 tak prefetch 8n par kyon ruki? Bada prefetch matlab bada minimum burst = wasted bandwidth; DDR4 ne bank groups use kiye.
DDR5 effectively 16n prefetch tak kaise pohonchta hai? Ye har channel ko do independent 32-bit subchannels mein split karta hai, har ek 8n prefetch ke saath.
64-bit channel par DDR4-3200 ki peak bandwidth compute karo. 3200 MT/s × 8 bytes = 25.6 GB/s.
"PC3-12800" ka matlab kya hai? DDR3 module jiska peak bandwidth 12800 MB/s hai (= DDR3-1600).
DDR3-1600 actually kitni core clock par run karta hai? 200 MHz (1600 ÷ 2 edges ke liye ÷ 4, 8n prefetch ke liye).
SDR→DDR5 mein operating voltage kaise evolve hui? 3.3 → 2.5 → 1.8 → 1.5 → 1.2 → 1.1 V (power save karne ke liye har generation mein girta hai).
Same MT/s par DDR5 aur DDR4 real performance mein kyon differ kar sakte hain? DDR5 ke dual subchannels zyada parallelism/concurrency dete hain, stalls reduce karte hain equal peak bandwidth ke bawajood.
reads chunk once, streams fast
same slow core, faster IO
