Row - column addressing and sense amplifiers

4.1.5 · Hardware › Memory Technologies

Chapter: Memory Technologies — ek chip millions mein se EK bit kaise dhundti hai, aur itne tiny signal ko kaise read karti hai jo barely measure ho sake.

Core Problem (WHY ye exist karta hai)

WHAT: Anatomy

Figure — Row - column addressing and sense amplifiers

HOW: Decoders pin count kyun kam karte hain

Derivation — zaruri pins. Maano array mein $N = R \times C$ bits hain.

$R$ rows mein se 1 pick karne ke liye $lo g_{2} R$ address bits chahiye.
$C$ columns mein se 1 pick karne ke liye $lo g_{2} C$ address bits chahiye.
Total address bits: $lo g_{2} R + lo g_{2} C = lo g_{2} (R C) = lo g_{2} N$ .

$address pins = lo g_{2} N$

Ye step kyun? Har independent binary bit itni lines double kar deti hai jo tum naam de sakte ho, isliye address hone wali cheezein hain $2^{(bits)}$ ; invert karo toh $lo g_{2}$ milta hai.

Square array pins-per-side minimize karta hai. $lo g_{2} N$ address bits ko row + column mein split karne ke liye, aur agar hum aage same pins ko row phir column ke liye time-multiplex bhi karna chahte hain (jaisa real DRAM RAS/CAS ke saath karta hai), toh ek shared bus ke liye pin count tab minimize hota hai jab $R = C = N$ :

$shared address pins = \frac{1}{2} lo g_{2} N = lo g_{2} N .$

HOW: DRAM cell padhna, step by step

Derivation — sense voltage. Read se pehle, bitline precharged hoti hai $V_{D D} /2$ tak aur phir float hoti hai. Storage cell ya toh $V_{D D}$ (logic 1) ya $0$ (logic 0) hold karta hai.

Jab wordline on hota hai, cell aur bitline charge share karte hain. Pehle ka total charge = baad ka charge, $Q = C V$ use karte hue:

$C_{s} V_{ce l l} + C_{b} \cdot \frac{V _{D D}}{2} = (C_{s} + C_{b}) V_{f ina l}$

Final bitline voltage ke liye solve karo:

$V_{f ina l} = \frac{C _{s} V _{ce l l} + C _{b} \frac{V _{D D}}{2}}{C _{s} + C _{b}}$

Signal jo sense amp dekhta hai wo precharge point $V_{D D} /2$ se deviation hai:

$Δ V = V_{f ina l} - \frac{V _{D D}}{2} = \frac{C _{s}}{C _{s} + C _{b}} (V_{ce l l} - \frac{V _{D D}}{2})$

Ye step kyun? Reference subtract karna sirf wo part isolate karta hai jo cell ki wajah se hua; reference bitline se jo common hai wo cancel ho jaata hai.

Sense amplifier ka kaam (differential):

Precharge bitline (BL) aur uska complement ( $\overline{BL}$ ) $V_{D D} /2$ tak.
Wordline activate karo → BL $Δ V$ se upar ya neeche nudge hoti hai; $\overline{BL}$ reference pe rehti hai (ya vice-versa, dummy cell use karke).
Cross-coupled latch enable karo (do back-to-back inverters). Positive feedback jo bhi line upar hai use $V_{D D}$ tak aur doosri ko $0$ tak drive karta hai.
Restore/refresh: ab full-swing BL abhi bhi cell se open access transistor ke through connected hai, isliye cell ka capacitor apni original value tak recharge ho jaata hai. (DRAM padhna destructive hai; sense amp use repair karta hai.)

Common Mistakes (Steel-manned)

Recall Ise 12 saal ke bache ko samjhao (click to reveal)

Socho ek badi apartment building jahan har apartment mein paani ki ek boond hai (wo memory bit hai). Har apartment tak pipe nahi daud sakti — billions hain. Toh tum kehte ho "Floor 12" (poore floor ki hallway light on ho jaati hai = wordline) aur "Apartment 8" (wo column pick hai). Ab tiny paani ki boond ek bahut lambi khaali pipe mein trickle karti hai (bitline) aur almost gayab ho jaati hai. Pipe ke neeche ek special helper (sense amplifier) itna sensitive hai ki bol sakta hai "drop TTHA" versus "kuch NAHI tha", zor se sunata hai taaki sab sunein (full 0 ya 1), aur phir — kyunki dekhne se boond use ho gayi — boond wapas apartment mein daalta hai taaki wo khoye na. Ye aakhri wapas daalna hi wajah hai ki hum kehte hain is memory ko padhna use mitata hai jab tak refill na karo.

Flashcards

Memory cells 2D grid mein kyun arrange hoti hain line ki jagah?

Wires share karne ke liye — ek grid ko sirf

lo g_{2} R + lo g_{2} C

address bits chahiye na ki har cell ke liye ek wire, jisse billion-bit chips possible hoti hain.

Row decoder physically kya karta hai?

Row address bits leta hai aur exactly ek wordline high karta hai, us row ki har cell ke access transistors on karta hai.

Wordline vs bitline kya hote hain?

Wordline = horizontal row-select control wire; Bitline = vertical column data wire jo us column ki saari cells share karti hain.

DRAM mein sense amplifier kyun zaruri hai?

Cell ka charge badi bitline pe share hone par sirf tens of mV produce karta hai; sense amp is tiny swing ko full logic level tak amplify karta hai.

Charge-sharing sense-signal formula do.

Δ V = \frac{C _{s}}{C _{s} + C _{b}} (V_{ce l l} - \frac{V _{D D}}{2})

Bitlines ko

V_{D D} /2

tak precharge kyun karte hain?

Ye read signal ko 0 aur 1 ke liye symmetric (

\pm Δ V

) banata hai, resolve karne ke liye chhota swing chahiye, aur differential sensing enable karta hai.

RAS aur CAS kya hain?

Row Address Strobe aur Column Address Strobe — SAME multiplexed pins pe pehle row phir column address latch karte hain.

N

bits ke liye kitne address pins (multiplexed, square array)?

\frac{1}{2} lo g_{2} N

DRAM read ko destructive kyun kehte hain?

Cell ko bitline se connect karna uska charge share away kar deta hai, original value kho jaati hai; sense amp ko wapas write karna padta hai.

Storage capacitor

C_{s}

bahut bada kyun nahi banate?

Signal

Δ V

saturate ho jaata hai jab

C_{s} \to C_{b}

, lekin bada

C_{s}

area waste karta hai aur density kill karta hai; instead bitlines ko short rakhte hain.

Sense amp ke andar tiny signal ko full swing tak kaun resolve karta hai?

Ek cross-coupled inverter latch positive feedback use karke jo line upar ho use

V_{D D}

tak aur doosri ko

0

tak drive karta hai.

Connections

DRAM cell structure (1T1C) — tiny charge $C_{s}$ ka source.
Memory refresh and retention time — sense amps wapas kyun write karte hain / kitni baar.
SRAM 6T cell — non-destructive read, koi refresh nahi chahiye, sensing se contrast karo.
Address decoders and multiplexers — row/column select ke peeche $n \to 2^{n}$ logic.
Memory banking and interleaving — $C_{b}$ small rakhne ke liye arrays split karna.
CAS latency and memory timing — RAS/CAS multiplexing par built timing.