Foundations — DRAM 1T1C cell structure

This page assumes you have seen none of the notation. We build every letter, every symbol, and every picture from scratch, in an order where each one leans only on the ones before it. By the end you will be able to read the parent note line by line without ever meeting a surprise.

1. Charge — the stuff we are storing

Picture a bucket. The water level is not the charge — the total water is the charge. Empty bucket = no charge = a stored 0. Full bucket = lots of charge = a stored 1.

Why the topic needs it: the entire "bit" is a quantity of charge. If you do not have a clear mental picture of "charge = amount of stuff in the bucket," none of the later formulas mean anything.

2. Voltage — how "full" the bucket feels

Two buckets can hold different amounts of water yet have the same level if one is wider. Voltage is the level; charge is the total water. That distinction is the whole reason capacitors matter (next section).

Why the topic needs it: the parent note calls a "1" the state "near $V_{DD}$" and a "0" the state "near $0$." Those are voltages — water levels — not charges. Reading a bit means measuring a voltage.

3. $V_{DD}$ — the "full" reference level

Everything else is measured against two marks: $0\text{ V}$ (empty) and $V_{DD}$ (full). Halfway up is $\frac{V_{DD}}{2}$, which will become the crucial "starting line" for reading.

Why the topic needs it: logic 1 ≈ $V_{DD}$, logic 0 ≈ $0$, and the bitline gets pre-set to $\frac{V_{DD}}{2}$. Without $V_{DD}$ as a yardstick these have no meaning.

4. The capacitor $C_s$ — the bucket itself

The defining law connects our first three symbols:

Why this tool and not another? We need a single relation that links "how full it looks" ($V$, what we can measure) to "how much stuff is inside" ($Q$, the actual bit). $Q=CV$ is exactly that link, and it is linear — double the level, double the charge — which keeps all later algebra simple. This is the master equation of the whole topic; see Capacitor Q=CV.

Why $C_s$ is deliberately tiny: a small bucket packs into a small area, so you fit billions of them on a chip. Small area is the entire point of DRAM density (the parent note's $6F^2$ / $4F^2$ goal).

5. The transistor — the tap

Why the topic needs it: the "1T" in 1T1C is this one transistor. It is the only moving part — it connects the bucket to the outside world during read/write, and isolates it (traps the charge) the rest of the time.

6. Wordline and Bitline — the two control wires

Think of a grid: horizontal wordlines pick which row of taps to open; vertical bitlines carry the water for each column. See Bitline and Wordline Architecture.

Why the topic needs it: every operation is phrased as "raise WL, drive BL." These are the two knobs you turn to talk to a cell.

7. $C_{BL}$ — the giant tank the bitline secretly is

Why the topic needs it: reading pours the tiny cup into this huge tank. Because the tank dwarfs the cup, the water level barely moves — which is exactly why reads are hard and need amplification. This inequality is the reason Sense Amplifiers exist.

8. Charge conservation — why reads are just arithmetic

Because charge is conserved, connecting $C_s$ (at level $V_{cell}$) to $C_{BL}$ (at level $\frac{V_{DD}}{2}$) gives one shared final level $V_{final}$:

$\underset{\text{charge before}}{\underbrace{C_s{V}_{cell}+C_{BL}\frac{V_{DD}}{2}}}=\underset{\text{charge after}}{\underbrace{(C_s+C_{BL})V_{final}}}$

Why this tool and not another? The transistor merely connects two capacitors; it invents nothing. When nothing is created or destroyed, the honest bookkeeping is conservation — "what went in must equal what came out." That is why the parent derives everything from this one balance instead of tracking currents.

9. The subtraction $V_{cell}-\frac{V_{DD}}{2}$ — the "signal"

From the balance in §8, algebra gives:

$\Delta V=V_{final}-\frac{V_{DD}}{2}=\frac{C_s}{C_s+C_{BL}}\left(V_{cell}-\frac{V_{DD}}{2}\right)$

• If the cell held a 1 ($V_{cell}>\frac{V_{DD}}{2}$): the bracket is positive → BL nudges up.
• If the cell held a 0 ($V_{cell}<\frac{V_{DD}}{2}$): the bracket is negative → BL nudges down.
• The fraction $\frac{C_s}{C_s+C_{BL}}$ is a small number (cup ÷ tank), so the nudge is only tens of millivolts.

Why start reading from $\frac{V_{DD}}{2}$? So that a "1" and a "0" push the bitline by equal and opposite amounts — perfectly symmetric — which is exactly what a differential sense amp wants to compare against.

10. The exponential $e^{-t/(R_{leak}{C}_s)}$ — why the bucket forgets

$V_{cell}(t)=V_{DD}{e}^{-t/(R_{leak}{C}_s)}$

Why an exponential and not a straight line? A leaking capacitor loses charge in proportion to how full it still is — a fuller bucket pushes harder, so it leaks faster. "Rate of loss ∝ current amount" is the exact signature of exponential decay (its rule $C\frac{dV}{dt}=-V/R_{leak}$ says precisely that). No other simple curve has that self-slowing property.

Why the topic needs it: this decay is why DRAM must refresh — read-and-rewrite every ≈64 ms before the level drops below what the sense amp can detect. The "D" in DRAM = Dynamic = "keeps changing, must be topped up."

Prerequisite map

Equipment checklist

Test yourself — cover the right side and answer each before revealing.

Connections

• Capacitor Q=CV — the master law built in §4.
• Charge Sharing — the conservation idea of §8.
• Bitline and Wordline Architecture — the two control wires of §6.
• Sense Amplifiers — why the tiny $\Delta V$ of §9 must be amplified.
• DRAM Refresh — the consequence of §10's decay.
• SRAM 6T cell — the denser-vs-faster counterpart to this cell.
• Hinglish version