DRAM 1T1C cell structure: Worked examples — Hardware deep dive

This page is the exhaustive drill for the 1T1C cell. The parent note gave you the formulas. Here we throw every kind of input at them — a full "1", a full "0", the leaky in-between, the degenerate cases where a capacitor is zero, the limiting case where the bitline is infinitely huge, a real-world timing problem, and an exam-style twist. Nothing should surprise you after this.

Before we start, here are the only three formulas we use, each already earned in the parent:

Standard numbers we reuse (from the parent's examples):

$C_{s} = 20 fF$ , $C_{B L} = 200 fF$ , $V_{D D} = 1.2 V$ , so precharge $= V_{D D} /2 = 0.6 V$ .

The scenario matrix

Every question this topic can ask falls into one of these case classes. Each row below is covered by at least one worked example.

#	Case class	What makes it distinct	Example
A	Read a full "1"	$V_{ce l l} = V_{D D}$ , swing is positive	Ex 1
B	Read a full "0"	$V_{ce l l} = 0$ , swing is negative	Ex 2
C	*Read a decayed* bit**	$V_{ce l l}$ between the extremes — is it still readable?	Ex 3
D	Degenerate: $C_{s} \to 0$	no storage → zero signal (why cells can't shrink forever)	Ex 4 (part D)
E	Limiting: $C_{B L} \to \infty$	infinitely long bitline → signal vanishes	Ex 4 (part E)
F	Charge / electron count	$Q = C_{s} V$ , "how many electrons is a bit?"	Ex 5
G	Real-world timing	find refresh interval from a leakage decay	Ex 6
H	Exam twist: solve backwards	given a required $Δ V$ , find max allowable $C_{B L}$	Ex 7
I	Exam twist: worst-case bit	which stored value gives the smallest safety margin?	Ex 8

Case A — Read a full "1"

Worked example

Statement. Cell holds a "1": $V_{ce l l} = 1.2 V$ . Bitline precharged to $0.6 V$ . Find the swing $Δ V$ and the final bitline voltage.

Forecast: Will BL move up or down, and by roughly how much — volts, or millivolts?

Identify the tool. This is charge sharing → Tool 2. Why this step? The transistor connects $C_{s}$ to $C_{B L}$ ; nothing is created, so charge conservation (Tool 2) is exactly the right instrument.
Compute the divider factor $\frac{C _{s}}{C _{s} + C _{B L}} = \frac{20}{220} = 0.0909$ . Why this step? This factor is how much of the cell's "voltage message" survives dilution into the big bitline. It's small because $C_{B L} ≫ C_{s}$ .
Compute the voltage difference $V_{ce l l} - \frac{V _{D D}}{2} = 1.2 - 0.6 = + 0.6 V$ . Why this step? The cell only pushes the bitline relative to the precharge level. A "1" sits above $0.6$ , so this is positive.
Multiply: $Δ V = 0.0909 \times 0.6 = + 0.0545 V = + 54.5 mV$ . Why this step? The swing formula is (surviving fraction) × (voltage message); multiplying the two numbers we just found gives the actual nudge the sense amp will see.
Final BL: $V_{f ina l} = 0.6 + 0.0545 = 0.6545 V$ . Why this step? $Δ V$ is measured from the precharge level, so the real bitline voltage is precharge plus the swing — that's the absolute value a voltmeter on BL would read.

Verify: Plug into the raw charge-sharing form: $\frac{20 ( 1.2 ) + 200 ( 0.6 )}{220} = \frac{24 + 120}{220} = \frac{144}{220} = 0.6545 V$ . ✓ Matches. A tiny positive nudge → sense amp reads 1.

Figure — Case A vs Case B swing. The horizontal blue dashed line is the precharge level $V_{D D} /2 = 0.6 V$ ; both bits start there. The magenta up-arrow is Case A: reading a "1" lifts the bitline to $0.6545 V$ (+54.5 mV). The violet down-arrow is Case B: reading a "0" drops it to $0.5455 V$ (−54.5 mV). The two arrows are mirror images about the dashed line — that visible symmetry is the whole reason we precharge to the midpoint.

Case B — Read a full "0"

Worked example

Statement. Same caps, but $V_{ce l l} = 0 V$ (a "0"). Find $Δ V$ and final BL voltage.

Forecast: By symmetry with Case A, guess the sign and magnitude before computing.

Same tool, same factor. $\frac{20}{220} = 0.0909$ . Why this step? The divider depends only on the capacitors, not on the stored value — so it's identical to Case A.
Voltage difference: $0 - 0.6 = - 0.6 V$ . Why this step? A "0" sits below the precharge level, so the cell pulls the bitline down → negative.
Multiply: $Δ V = 0.0909 \times (- 0.6) = - 0.0545 V = - 54.5 mV$ . Why this step? Same surviving-fraction × voltage-message product as before; the negative message carries the negative sign straight into the swing, telling us BL drops.
Final BL: $0.6 - 0.0545 = 0.5455 V$ . Why this step? Again the absolute bitline reading is precharge plus swing; here the swing is negative, so we subtract to land below the midline.

Verify: Raw form: $\frac{20 ( 0 ) + 200 ( 0.6 )}{220} = \frac{120}{220} = 0.5455 V$ . ✓ Exactly mirror-image of Case A around $0.6 V$ (the violet down-arrow in the Case-A/B figure above). This symmetry is why we precharge to $V_{D D} /2$ .

Case C — Read a decayed bit (the in-between)

Worked example

Statement. A "1" was written at $1.2 V$ , but leakage has drained it to $V_{ce l l} = 0.75 V$ by the time we read. Same caps. Is it still detected as a "1", and with how much margin?

Forecast: The bit is half-drained. Will the swing still be positive? Will the sense amp still see it?

Tool 2 again, factor $= 0.0909$ . Why this step? It's still charge sharing between the same two capacitors, so the surviving-fraction factor is unchanged — only the stored voltage differs.
Voltage difference: $0.75 - 0.6 = + 0.15 V$ . Why this step? Even a weak "1" is still above midline — but only by $0.15$ , not $0.6$ . The message shrank to a quarter.
Multiply: $Δ V = 0.0909 \times 0.15 = + 0.01364 V = 13.6 mV$ . Why this step? The same product (fraction × message) turns the shrunken message into the shrunken swing the sense amp must catch.

Verify: Raw form: $\frac{20 ( 0.75 ) + 200 ( 0.6 )}{220} = \frac{15 + 120}{220} = \frac{135}{220} = 0.6136 V$ ; minus $0.6$ gives $0.01364 V$ . ✓

Interpretation. Still positive, still a "1" — but only $13.6 mV$ of margin versus $54.5 mV$ fresh. If the sense-amp threshold were, say, $15 mV$ , this bit would be misread as 0. This is exactly why DRAM Refresh exists: refresh must fire while $Δ V$ is still comfortably above the detectable margin.

Cases D & E — Degenerate & limiting inputs

Worked example

Statement (two edge cases). (D) What is $Δ V$ if the storage capacitor shrinks to nothing, $C_{s} \to 0$ ? (E) What is $Δ V$ if the bitline grows infinitely long, $C_{B L} \to \infty$ ? (Take a "1", $V_{ce l l} = 1.2$ .)

Forecast: Both are "the cell can't be heard" cases — but predict which physical extreme kills the signal.

Case D — compute the voltage difference first: $V_{ce l l} - \frac{V _{D D}}{2} = 1.2 - 0.6 = + 0.6 V$ . Why this step? Even in a degenerate case we build the swing formula piece by piece; the "voltage message" of a "1" is the same $+ 0.6 V$ we used in Case A, and it does not depend on $C_{s}$ , so it survives the shrinking cell unchanged.
Case D — substitute $C_{s} = 0$ into the divider factor: $\frac{C _{s}}{C _{s} + C _{B L}} = \frac{0}{0 + C _{B L}} = 0$ , hence $Δ V = 0 \times 0.6 = 0$ . Why this step? A cup with zero capacity holds zero charge ( $Q = 0 \cdot V = 0$ ), so it has nothing to say to the bitline. The divider factor collapses to zero and the swing vanishes exactly.
Physical meaning of D. This is the floor on cell size: shrink $C_{s}$ too far and $Δ V$ falls below the sense-amp margin. It's why the storage capacitor is built tall (trench/stacked) to keep $C_{s}$ up while the footprint shrinks.
Case E — take the limit $C_{B L} \to \infty$ of the divider factor: $\frac{C _{s}}{C _{s} + C _{B L}} \to 0$ , so $Δ V \to 0$ . Why this step? An infinite tank swallows any cup without changing level. As the denominator grows without bound while the numerator stays fixed at $C_{s}$ , the fraction is squeezed to zero.
A concrete taste of E: at $C_{B L} = 2000 fF$ (10× longer bitline), factor $= \frac{20}{2020} = 0.00990$ , so $Δ V = 0.00990 \times 0.6 = 5.94 mV$ — a "1" barely whispering. Why this step? An abstract limit is easy to distrust, so we plug in a real 10× number to watch the signal collapse and confirm the trend the limit predicted.

Verify (E numeric): $\frac{20}{2020} \times 0.6 = 0.005941 V$ . ✓ Ten times longer bitline → roughly ten times weaker signal. This is the maths behind the mistake "bigger $C_{B L}$ is better" — it's the opposite.

Figure — signal vs bitline length. The orange curve plots the "1" swing $Δ V$ against the bitline capacitance $C_{B L}$ . The magenta dot marks our standard $C_{B L} = 200 fF$ (54.5 mV — healthy). The violet square marks the Case-E point at $C_{B L} = 2000 fF$ (only 5.94 mV — barely a whisper). Follow the curve rightward: it sags toward the zero line, the visual proof that a longer bitline shrinks the signal.

Case F — Charge & electron count

Worked example

Statement. How much charge sits on a cell holding "1", and how many electrons is that? $C_{s} = 20 fF$ , $V_{D D} = 1.2 V$ . (Electron charge $e = 1.602 \times 1 0^{- 19} C$ .)

Forecast: Guess the order of magnitude — is a bit thousands, millions, or billions of electrons?

Tool 1: $Q = C_{s} V = 20 \times 1 0^{- 15} \times 1.2 = 2.4 \times 1 0^{- 14} C = 24 fC$ . Why this step? The bit is the charge; $Q = C V$ converts the stored voltage into coulombs.
Count electrons: $N = \frac{Q}{e} = \frac{2.4 \times 1 0 ^{- 14}}{1.602 \times 1 0 ^{- 19}} \approx 1.498 \times 1 0^{5}$ . Why this step? Charge comes in electron-sized lumps, so dividing the total charge by one electron's charge counts how many lumps make up the bit.

Verify: $2.4 \times 1 0^{- 14} /1.602 \times 1 0^{- 19} = 149, 813 \approx 1.5 \times 1 0^{5}$ electrons. ✓

Interpretation. A whole bit is only ~150,000 electrons. Lose ~half to leakage and the "1" collapses — the tiny electron budget is the entire reason refresh timing is so tight.

Case G — Real-world refresh timing

Worked example

Statement. A cell starts at $V_{0} = 1.2 V$ . Leakage gives $R_{l e ak} = 2 \times 1 0^{15} Ω$ (2 petaohm — leakage is very small) and $C_{s} = 20 fF$ . The sense amp still reads "1" as long as $V_{ce l l} > 0.9 V$ . How long until we must refresh?

Forecast: Milliseconds? Microseconds? Seconds? Guess the scale first.

Time constant: $τ = R_{l e ak} C_{s} = 2 \times 1 0^{15} \times 20 \times 1 0^{- 15} = 40 s$ . Why this step? $τ$ (Tool 3) sets the natural decay speed — after $τ$ seconds the voltage falls to $1/ e$ (~37%) of start.
Set the decay to the threshold: $0.9 = 1.2 e^{- t /40}$ . Why this step? Refresh must happen before the voltage crosses the margin, so we solve for the moment it hits $0.9 V$ .
Isolate the exponential: divide both sides by $1.2$ : $e^{- t /40} = \frac{0.9}{1.2} = 0.75$ . Why this step? We want $t$ , which is trapped inside the exponent; first we get the exponential alone on one side so we can undo it.
Take the natural log of both sides: $- \frac{t}{40} = ln (0.75) = - 0.2877$ . Why this step? $ln$ is the exact inverse of $e^{(\cdot)}$ — it's the tool that frees $t$ from the exponent. It answers "how many time-constants to reach this fraction?"
Multiply both sides by $- 40$ : $t = (- 40) \times (- 0.2877) = + 11.5 s$ . Why this step? $t$ still has a $- \frac{1}{40}$ coefficient attached; multiplying by $- 40$ cancels it. The two minus signs multiply to a plus, so time comes out positive — as any real elapsed time must.

Verify: $1.2 e^{- 11.5/40} = 1.2 e^{- 0.2877} = 1.2 \times 0.75 = 0.90 V$ . ✓ We must refresh well within ~11.5 s.

Reality check on units. Real DRAM refreshes at ~ $64 ms$ , far tighter than this idealized 11.5 s — because real leakage paths (junction + subthreshold) are far worse than this toy $R_{l e ak}$ , and worst-case (hottest, weakest) cells set the budget, not the average cell.

Case H — Exam twist: solve the swing formula backwards

Worked example

Statement. A sense amp needs at least $Δ V = 40 mV$ to reliably detect a "1" ( $V_{ce l l} = 1.2$ , precharge $0.6$ ). With $C_{s} = 20 fF$ fixed, what is the maximum allowable $C_{B L}$ ?

Forecast: Longer bitlines mean weaker signal — so there must be a ceiling on $C_{B L}$ . Above or below the standard 200 fF?

Start from the swing formula: $Δ V = \frac{C _{s}}{C _{s} + C _{B L}} (V_{ce l l} - \frac{V _{D D}}{2})$ . Why this step? The exam gives us the output ( $Δ V$ ) and wants an input ( $C_{B L}$ ), so we begin from the relation that links them and rearrange toward $C_{B L}$ .
Divide both sides by the voltage difference $(V_{ce l l} - \frac{V _{D D}}{2})$ to strip it off the right: $\frac{Δ V}{V _{ce l l} - \frac{V _{D D}}{2}} = \frac{C _{s}}{C _{s} + C _{B L}} .$ Why this step? We're peeling factors off the right-hand side one at a time; removing the voltage message leaves the pure capacitor fraction, which is the part that actually contains $C_{B L}$ .
Flip both sides (take reciprocals): $\frac{V _{ce l l} - \frac{V _{D D}}{2}}{Δ V} = \frac{C _{s} + C _{B L}}{C _{s}} .$ Why this step? $C_{B L}$ is stuck inside a denominator on the right; taking the reciprocal of both sides brings the $(C_{s} + C_{B L})$ sum up into the numerator, where we can finally reach and isolate it.
Multiply both sides by $C_{s}$ : $C_{s} + C_{B L} = \frac{C _{s} ( V _{ce l l} - \frac{V _{D D}}{2} )}{Δ V} .$ Why this step? This clears the lone $C_{s}$ in the denominator on the right, leaving the whole sum $C_{s} + C_{B L}$ alone on the left — one subtraction away from the answer.
Plug in the numbers: $C_{s} + C_{B L} = \frac{20 \times 0.6}{0.040} = \frac{12}{0.040} = 300 fF$ . Why this step? With $C_{B L}$ almost isolated, substituting the known values ( $C_{s} = 20$ , message $= 0.6 V$ , required $Δ V = 0.040 V$ ) gives the total capacitance the margin can tolerate.
Subtract $C_{s}$ : $C_{B L, m a x} = 300 - 20 = 280 fF$ . Why this step? We wanted $C_{B L}$ by itself, so we remove the cell's own contribution from the sum — the last algebraic move that frees $C_{B L}$ .

Verify: Forward check with $C_{B L} = 280$ : $Δ V = \frac{20}{300} \times 0.6 = 0.06667 \times 0.6 = 0.040 V = 40 mV$ . ✓ Any bitline longer than $280 fF$ pushes the signal below the sense-amp's margin.

Case I — Exam twist: which stored value is worst-case?

Worked example

Statement. Because the leaky "off" transistor slowly drags the storage node toward the bitline's precharge level, suppose a written "1" ( $1.2 V$ ) has decayed to $0.70 V$ , while a written "0" ( $0 V$ ) has crept up to $0.45 V$ . Which bit is closer to being misread, and by how much margin?

Forecast: A "1" only decays down; a "0" only creeps up. Both march toward $0.6 V$ . Which one is in more danger here?

Swing of the decayed "1": $Δ V_{1} = \frac{20}{220} (0.70 - 0.6) = 0.0909 \times 0.10 = + 9.09 mV$ . Why this step? The same charge-sharing product (Tool 2) gives this weak "1"'s nudge above the midline — that nudge is its safety margin against a misread.
Swing of the crept "0": $Δ V_{0} = \frac{20}{220} (0.45 - 0.6) = 0.0909 \times (- 0.15) = - 13.6 mV$ . Why this step? Same formula for the crept "0"; the negative sign confirms it still pulls BL down (so it still reads as "0"), and the magnitude is its safety margin.
Compare magnitudes: $∣Δ V_{1} ∣ = 9.09 mV < ∣Δ V_{0} ∣ = 13.6 mV$ . Why this step? Margin is distance from the midline regardless of direction, so we compare absolute values; the smaller one is the bit nearest to a misread.

Verify: $\frac{20}{220} \times 0.10 = 0.009091 V$ and $\frac{20}{220} \times 0.15 = 0.013636 V$ . ✓ The decayed "1" has the smaller margin (9.1 mV) → it flips first. This is why in practice the retention time of the weak "1" dominates the refresh budget.

Recall Quick self-test on the whole matrix

Read of a fresh "1" swing sign? ::: Positive (+54.5 mV). Read of a fresh "0" swing sign? ::: Negative (−54.5 mV). What happens to $Δ V$ as $C_{s} \to 0$ ? ::: It goes to zero — no charge, no signal. What happens to $Δ V$ as $C_{B L} \to \infty$ ? ::: It goes to zero — infinite tank swallows the cup. Electrons in one "1" bit at 20 fF, 1.2 V? ::: About $1.5 \times 1 0^{5}$ . How do you undo the exponential to get refresh time? ::: Take the natural log, $ln$ . Max $C_{B L}$ for a 40 mV margin (20 fF cell, 1.2 V)? ::: 280 fF. Which decayed bit flips first, a weak "1" or a crept "0" (here)? ::: The weak "1" (smaller margin, 9.1 mV).

Connections

DRAM 1T1C cell structure — the parent this drill expands.
Charge Sharing — the mechanism behind Cases A–E and H–I.
Sense Amplifiers — the device whose margin sets Cases C, H, I.
DRAM Refresh — the timing budget of Case G.
Capacitor Q=CV — Tool 1, used in Cases D–F.
Bitline and Wordline Architecture — why $C_{B L}$ is large (Case E).