DRAM 1T1C cell structure: Question bank — Hardware deep dive

Remember the whole cast of characters before you start:

$C_{s}$ = the tiny storage capacitor (the water cup).
$C_{B L}$ = the bitline capacitance (the giant tank the cup pours into).
$V_{D D}$ = the supply voltage; a full cup sits near $V_{D D}$ , an empty cup near $0$ .
$Δ V$ = how far the bitline moves away from its precharged rest point of $V_{D D} /2$ .

True or false — justify

True or false: a DRAM cell physically stores the number 1 or 0 as a digit.

False. It stores charge, a continuous voltage on

C_{s}

; "1" and "0" are just labels for "near

V_{D D}

" and "near

0

", and the sense amp decides which side of

V_{D D} /2

we landed on.

True or false: the access transistor stores the bit.

False. The transistor is only the tap (a switch); the bit lives as charge on the capacitor

C_{s}

. The transistor's job is to isolate that charge when the wordline is off.

True or false: reading a DRAM cell leaves the stored data untouched.

False. Reading connects

C_{s}

to the huge

C_{B L}

; charge sharing dilutes

V_{ce l l}

toward

V_{D D} /2

, wrecking the bit — so it is destructive and must be rewritten.

True or false: making

C_{B L}

larger gives a stronger read signal.

False. Since

Δ V = \frac{C _{s}}{C _{s} + C _{B L}} (V_{ce l l} - \frac{V _{D D}}{2})

, a bigger

C_{B L}

shrinks the fraction and weakens the swing. Short bitlines are better.

True or false: refresh is only necessary because DRAM transistors are poorly manufactured.

False. Even an ideal-ish transistor has junction and subthreshold leakage, and

C_{s}

is deliberately tiny for density. Leaky-by-design + tiny charge = inevitable decay, so refresh is fundamental, not a defect.

True or false: precharging the bitline to

0

V would work just as well as

V_{D D} /2

False. From

V_{D D} /2

a "1" swings up and a "0" swings down symmetrically, halving the worst-case swing and giving a differential sense amp a clean reference. From

0

V there is no symmetry and a "0" would produce essentially no signal.

True or false: after a read, the cell voltage is restored automatically by the capacitor.

False. Nothing self-heals; the sense amp must actively drive the bitline back to a full rail and rewrite the bit through the still-open wordline.

True or false: DRAM is "dynamic" because its data changes while you read it.

Partly a trap — the "D" means data must be periodically refreshed due to leakage. The destructive read is a separate phenomenon; both involve change, but "Dynamic" refers to the refresh requirement.

True or false: 1T1C is used instead of SRAM's 6T mainly because it is faster.

False. It is used for density and cost (fewer transistors → more bits per chip). It is actually slower than 6T SRAM; that is the trade you accept.

Spot the error

Find the flaw: "Lower the wordline first, then drive the bitline — that way the charge is safely trapped before writing."

Backwards. If WL is lowered first the tap is closed and no new charge can reach

C_{s}

, so nothing gets written. You drive BL, raise WL to let charge flow, then lower WL last to trap it.

Find the flaw: "The signal swing

Δ V

equals

V_{ce l l} - V_{D D} /2

It omits the charge-sharing divider

\frac{C _{s}}{C _{s} + C _{B L}}

. Because

C_{B L} ≫ C_{s}

, the real swing is tens of millivolts, not the full half-rail.

Find the flaw: "Charge sharing creates extra charge on the bitline to amplify the read."

No charge is created; the read obeys charge conservation. The total charge is merely redistributed across

C_{s} + C_{B L}

, which dilutes the voltage — amplification is the separate job of the sense amp.

Find the flaw: "Since a stored '1' is at

V_{D D}

and the bitline sits at

V_{D D} /2

, reading a '1' pulls the bitline all the way to

V_{D D}

The bitline only rises by

Δ V = \frac{C _{s}}{C _{s} + C _{B L}} \cdot \frac{V _{D D}}{2}

, a small nudge upward, because the tiny cup cannot fill the huge tank. The sense amp then drives it to the rail.

Find the flaw: "A logic '0' means the storage node is at exactly

V_{D D} /2

A "0" is stored near ==

0

V== (or whatever low level the design uses);

V_{D D} /2

is only the precharge rest voltage of the bitline, not the stored-0 level. Confusing the two loses all read margin.

Find the flaw: "Refresh reads a cell and, if it finds a '1', tops it up; a stored '0' needs no refresh."

Refresh re-reads and rewrites every cell unconditionally, because the read itself is destructive. A "0" must also be actively restored so leakage doesn't drift it upward.

Why questions

Why is the storage node made to "float" after writing, rather than being held by a driver?

A floating (isolated) node holds charge with nothing to bleed it off quickly, giving retention. Holding it with a driver would need extra transistors, killing the density advantage that justifies DRAM.

Why does the huge

C_{B L} ≫ C_{s}

ratio force the existence of a sense amplifier?

Because the divider

\frac{C _{s}}{C _{s} + C _{B L}}

crushes the read signal to tens of mV — too small for downstream logic — so a sense amp must ==amplify

Δ V

== back to a full logic level.

Why is

Q = C_{s} V

the right starting relation for reasoning about a DRAM bit?

Because the bit is the voltage on

C_{s}

, and $Q=CV$ links that voltage to the concrete quantity of charge — letting us reason about how much charge leaks away before the bit becomes unreadable.

Why does refresh get shorter (e.g. 32 ms) at high temperature?

Leakage currents rise sharply with temperature, so

V_{ce l l}

decays faster; the top-up must happen sooner to catch the bit before it falls past the sense margin.

Why does a longer bitline (touching more cells) hurt read reliability?

A longer wire has larger

C_{B L}

, which shrinks

Δ V

per the divider. Designers segment arrays to keep

C_{B L}

modest relative to

C_{s}

Edge cases

Edge case: what does the sense amp see if the cell already sits exactly at

V_{D D} /2

before reading?

Then

V_{ce l l} - V_{D D} /2 = 0

, so

Δ V = 0

— the read produces no signal and the bit is ambiguous. This is exactly the failure state that leakage drives cells toward, and why refresh must act before it happens.

Edge case: what is

Δ V

if a manufacturing fault makes

C_{s} = 0

(dead/open capacitor)?

With

C_{s} = 0

the fraction

\frac{C _{s}}{C _{s} + C _{B L}} = 0

, so

Δ V = 0

regardless of the intended bit — the cell is stuck / unreadable, indistinguishable from a permanently mid-level node.

Edge case: what happens to the swing in the imaginary limit

C_{s} ≫ C_{B L}

The divider

\frac{C _{s}}{C _{s} + C _{B L}} \to 1

, so

Δ V \to V_{ce l l} - V_{D D} /2

— a huge, non-destructive-ish read. This is why SRAM-like robustness costs area; real DRAM lives in the opposite (tiny-

C_{s}

) regime.

Edge case: if the wordline is never lowered after a write, is the bit still "stored"?

No. With WL held on the tap stays open, so the node is not isolated; charge can flow back out to the bitline and the value is not retained — trapping requires closing the transistor.

Edge case: reading a "1" versus a "0" — do they move the bitline by the same magnitude?

Yes, by symmetry about

V_{D D} /2

: a "1" gives

+ Δ V

and a "0" gives

- Δ V

of equal size. That balanced ==

\pm

swing== is precisely why precharge sits at the midpoint.

Connections

Charge Sharing — the mechanism behind every "destructive read" trap here.
Sense Amplifiers — why a tiny $Δ V$ still yields a solid bit.
DRAM Refresh — the answer to every "why does it forget" trap.
Bitline and Wordline Architecture — why $C_{B L}$ is big and how segmentation fights it.
SRAM 6T cell — the non-destructive counterpart these traps contrast against.