Everything here rests on three tools you already met in the parent note:

A quick reminder of the units, because half of all DRAM errors are unit slips:

Level 1 — Recognition

Goal: name the parts and read a value straight off a formula, no algebra.

Exercise 1.1

State which physical line connects to (a) the transistor gate, and (b) the transistor source/drain that carries the bit in and out.

Recall Solution 1.1

(a) The wordline (WL) connects to the gate — raising it "opens the tap". (b) The bitline (BL) connects to the source/drain — it carries charge in during a write and out during a read. See Bitline and Wordline Architecture for how these run across the array.

Exercise 1.2

A cell holds logic 1. Roughly what voltage is on the storage node, and roughly what voltage is on it for logic 0 (in the $V_{D D} /2$ precharge scheme)?

Recall Solution 1.2

Logic 1 → storage node near $V_{D D}$ (charged bucket). Logic 0 → storage node near $0$ V (empty bucket). The bitline is precharged to $V_{D D} /2$ ; that half-level is a reference, not the stored value.

Exercise 1.3

Without computing, look at $Δ V = \frac{C _{s}}{C _{s} + C _{B L}} (V_{ce l l} - \frac{V _{D D}}{2})$ . If the cell stores a "1" (so $V_{ce l l} > V_{D D} /2$ ), will $Δ V$ be positive or negative? What about a "0"?

Recall Solution 1.3

The prefactor $\frac{C _{s}}{C _{s} + C _{B L}}$ is always positive (both caps positive). So the sign of $Δ V$ is the sign of $(V_{ce l l} - \frac{V _{D D}}{2})$ .

"1": $V_{ce l l} > V_{D D} /2$ → positive (bitline swings up).
"0": $V_{ce l l} < V_{D D} /2$ → negative (bitline swings down).

Level 2 — Application

Goal: plug numbers into the tools and get a value with correct units.

Exercise 2.1

$C_{s} = 25 fF$ , $C_{B L} = 250 fF$ , $V_{D D} = 1.0 V$ , cell holds a 1 ( $V_{ce l l} = 1.0$ ). Find $Δ V$ in millivolts.

Recall Solution 2.1

What: apply Tool 3. Why: the transistor connects $C_{s}$ to $C_{B L}$ , so signal swing is the only thing the sense amp sees. $Δ V = \frac{25}{25 + 250} (1.0 - 0.5) = \frac{25}{275} \times 0.5 = 0.04545 V \approx 45.5 mV$ The femtofarads cancel in the ratio — only their ratio matters, so we never convert to farads here.

Exercise 2.2

Same caps and $V_{D D}$ as 2.1, but the cell holds a 0 ( $V_{ce l l} = 0$ ). Find $Δ V$ .

Recall Solution 2.2

$Δ V = \frac{25}{275} (0 - 0.5) = - 0.04545 V \approx - 45.5 mV$ Equal magnitude, opposite sign to Exercise 2.1 — that symmetry is exactly why we precharge to $V_{D D} /2$ .

Exercise 2.3

$C_{s} = 25 fF$ , $V_{D D} = 1.0 V$ . How much charge $Q$ sits on a cell holding a 1? Give it in femtocoulombs.

Recall Solution 2.3

Why Tool 1 and not Tool 3? We want stored charge, not a bitline swing — that is the defining relation $Q = C V$ . $Q = C_{s} V_{D D} = 25 \times 1 0^{- 15} \times 1.0 = 2.5 \times 1 0^{- 14} C = 25 fC$

Level 3 — Analysis

Goal: reason about how the numbers behave, not just compute one.

Exercise 3.1

Keep $C_{s} = 25 fF$ , $V_{D D} = 1.0 V$ , cell = 1. Compute $Δ V$ for $C_{B L} = 100, 250, 500 fF$ . What trend do you see, and why does it matter for chip design? (See figure below.)

Recall Solution 3.1

Using $Δ V = \frac{25}{25 + C _{B L}} (0.5)$ :

$C_{B L} = 100$ : $\frac{25}{125} \times 0.5 = 0.1000 V = 100 mV$
$C_{B L} = 250$ : $\frac{25}{275} \times 0.5 = 0.04545 V \approx 45.5 mV$
$C_{B L} = 500$ : $\frac{25}{525} \times 0.5 = 0.02381 V \approx 23.8 mV$ Trend: bigger $C_{B L}$ → smaller swing (the curve in the figure falls). Why it matters: a long bitline touches many cells and grows $C_{B L}$ ; if the swing drops below the sense-amp margin the read fails. Designers segment the array to keep $C_{B L}$ small — see Sense Amplifiers.

Exercise 3.2

Define the charge-transfer ratio $β = \frac{C _{s}}{C _{s} + C _{B L}}$ . Show that when $C_{B L} ≫ C_{s}$ we can approximate $β \approx \frac{C _{s}}{C _{B L}}$ , and check the error for $C_{s} = 25$ , $C_{B L} = 250 fF$ .

Recall Solution 3.2

What: when $C_{B L}$ dominates, $C_{s} + C_{B L} \approx C_{B L}$ , so $β = \frac{C _{s}}{C _{s} + C _{B L}} \approx \frac{C _{s}}{C _{B L}}$ . Check: exact $β = \frac{25}{275} = 0.09091$ ; approximation $\frac{25}{250} = 0.1000$ . Relative error $= \frac{0.1000 - 0.09091}{0.09091} = 0.1 = 10%$ . The approximation over-estimates because we dropped the $+ C_{s}$ in the denominator, which was $\frac{25}{275} \approx 9%$ of the total.

Exercise 3.3

For the "1"-read the bitline ends at $V_{f ina l} = V_{D D} /2 + Δ V$ . Using $C_{s} = 25$ , $C_{B L} = 250$ , $V_{D D} = 1.0$ , find $V_{f ina l}$ and the new voltage left on the storage node after sharing (before the sense amp rewrites). Why does this prove the read is destructive?

Recall Solution 3.3

After sharing, both plates sit at the same voltage $V_{f ina l}$ (they are connected): $V_{f ina l} = \frac{C _{s} V _{ce l l} + C _{B L} \frac{V _{D D}}{2}}{C _{s} + C _{B L}} = \frac{25 ( 1.0 ) + 250 ( 0.5 )}{275} = \frac{150}{275} = 0.5455 V$ The storage node, which started at $1.0$ V, is now at $0.5455$ V. It got diluted toward $V_{D D} /2$ — the original "1" is largely gone. That is exactly why the sense amp must rewrite the bit (see DRAM Refresh).

Level 4 — Synthesis

Goal: combine charge, swing, leakage and refresh into one argument.

Exercise 4.1

A cell holds a "1": $C_{s} = 25 fF$ , $V_{D D} = 1.0 V$ , so $Q_{0} = 25 fC$ . Leakage bleeds charge at a constant rate of $0.1 fC/ms$ (approximate the decay as linear over the refresh window). The sense amp still reads "1" correctly as long as the node stays above $0.7 V$ . What is the longest safe refresh interval?

Recall Solution 4.1

Step 1 — voltage floor to charge floor. $Q_{min} = C_{s} V_{min} = 25 \times 0.7 = 17.5 fC$ . Step 2 — charge we may lose. $Δ Q = Q_{0} - Q_{min} = 25 - 17.5 = 7.5 fC$ . Step 3 — time to lose it. $t = \frac{Δ Q}{rate} = \frac{7.5 fC}{0.1 fC/ms} = 75 ms$ . So refresh must happen at least every 75 ms — comfortably explaining the standard ~64 ms guardband.

Exercise 4.2

Now model the same leakage as a true RC decay $V_{ce l l} (t) = V_{D D} e^{- t / (R_{l e ak} C_{s})}$ with $R_{l e ak} = 3 \times 1 0^{12} Ω$ (3 TΩ) and $C_{s} = 25 fF$ . Find the time for a "1" to fall from $1.0$ V to the same $0.7$ V floor. Compare to the linear estimate.

Recall Solution 4.2

Why exponential? A capacitor discharging through a resistor obeys $C \frac{d V}{d t} = - V / R_{l e ak}$ , whose solution is the exponential — the true physics of leakage. Time constant $τ = R_{l e ak} C_{s} = 3 \times 1 0^{12} \times 25 \times 1 0^{- 15} = 0.075 s = 75 ms$ . Set $0.7 = 1.0 e^{- t / τ}$ → $e^{- t / τ} = 0.7$ → $t = - τ ln (0.7) = 75 \times 0.35667 = 26.75 ms$ . So $t \approx 26.8 ms$ . The exponential model is much stricter than the linear one (75 ms) because decay is fastest at the start when $V$ is highest — the linear rate assumed the slow late-stage rate throughout.

Exercise 4.3

The chip has $8 \times 1 0^{9}$ cells and must refresh each every 64 ms. If refresh is spread evenly across the 64 ms window in rows of $2^{13} = 8192$ cells per refresh operation, how many refresh operations per second must the controller run?

Recall Solution 4.3

Step 1 — rows to refresh. $\frac{8 \times 1 0 ^{9}}{8192} = 976, 562.5 \to 976, 563$ rows (round up; you cannot do a fractional row). Step 2 — refresh cycles per second. All rows must be covered every 64 ms $= 0.064$ s, i.e. $\frac{1}{0.064} = 15.625$ full sweeps per second. $ops/s = 976, 563 \times 15.625 \approx 1.526 \times 1 0^{7} refresh operations per second.$ That is ~15 million refreshes every second — a real, continuous cost, which is why DRAM is called dynamic (see DRAM Refresh).

Level 5 — Mastery

Goal: edge cases, degenerate inputs, and why SRAM dodges all of this.

Exercise 5.1 (degenerate input)

What is the signal swing $Δ V$ if a cell holds a "0" at exactly $V_{ce l l} = V_{D D} /2$ ? Interpret physically why this is the worst possible cell state.

Recall Solution 5.1

$Δ V = \frac{C _{s}}{C _{s} + C _{B L}} (\frac{V _{D D}}{2} - \frac{V _{D D}}{2}) = 0.$ Zero swing. The cell already matches the precharge, so connecting it moves the bitline nowhere — the sense amp gets no signal and cannot decide 1 vs 0. This is why leakage that drags a "1" down toward $V_{D D} /2$ is fatal: as the node approaches $V_{D D} /2$ , the swing collapses to nothing.

Exercise 5.2 (limiting behaviour)

Take $Δ V = \frac{C _{s}}{C _{s} + C _{B L}} (V_{ce l l} - \frac{V _{D D}}{2})$ . Find the limit of $Δ V$ as (a) $C_{B L} \to \infty$ and (b) $C_{B L} \to 0$ . Interpret both.

Recall Solution 5.2

(a) As $C_{B L} \to \infty$ : $\frac{C _{s}}{C _{s} + C _{B L}} \to 0$ , so $Δ V \to 0$ . An infinitely large bitline is unmovable by one tiny cell — the read is impossible. (This is the extreme of Exercise 3.1's trend.) (b) As $C_{B L} \to 0$ : $\frac{C _{s}}{C _{s} + C _{B L}} \to 1$ , so $Δ V \to V_{ce l l} - \frac{V _{D D}}{2}$ . With no bitline capacitance the cell dumps its full voltage difference onto the line — the read would be perfect, but a real bitline touching many cells can never have zero capacitance.

Exercise 5.3 (case coverage: every stored value)

Fill the table for $C_{s} = 25$ , $C_{B L} = 250 fF$ , $V_{D D} = 1.0 V$ : for $V_{ce l l} = 1.0, 0.75, 0.5, 0.25, 0.0$ , give $Δ V$ and the sense-amp decision. Where is the decision boundary?

Recall Solution 5.3

$β = \frac{25}{275} = 0.09091$ . $Δ V = 0.09091 (V_{ce l l} - 0.5)$ :

$V_{ce l l} = 1.00$ : $Δ V = + 45.5 mV$ → reads 1
$V_{ce l l} = 0.75$ : $Δ V = + 22.7 mV$ → reads 1
$V_{ce l l} = 0.50$ : $Δ V = 0 mV$ → undecidable (boundary)
$V_{ce l l} = 0.25$ : $Δ V = - 22.7 mV$ → reads 0
$V_{ce l l} = 0.00$ : $Δ V = - 45.5 mV$ → reads 0 The decision boundary is $V_{ce l l} = V_{D D} /2$ : above it swings positive (1), below it swings negative (0). Precharging exactly there splits the two cases symmetrically.

Exercise 5.4 (synthesis vs SRAM)

In one paragraph, explain why an SRAM 6T cell does not need refresh or a destructive-read rewrite, tying it back to charge sharing.

Recall Solution 5.4

An SRAM cell stores its bit in a cross-coupled latch (two inverters holding each other) continuously driven by power — it is not a floating charge bucket, so there is no charge to leak away and nothing to top up: no refresh. When read, the latch actively drives the bitline rather than passively sharing charge, so the stored state is not diluted: non-destructive, no rewrite. The price is 6 transistors per bit instead of 1T1C, hence far lower density — the exact trade-off the parent note names.

Connections

DRAM 1T1C cell structure — parent note these exercises drill.
Charge Sharing · Capacitor Q=CV — the two tools every problem uses.
Sense Amplifiers — why a 45 mV swing is enough (and why 0 mV is fatal).
DRAM Refresh — the timing budget of L4.
SRAM 6T cell — the contrast in L5.
Bitline and Wordline Architecture — where WL/BL physically run.