SRAM 6T cell structure and operation: Worked examples

This deep dive takes the parent note and drills into every case the 6T cell can throw at you: both stored values, both operations, the degenerate "can't write / accidentally flipped" failures, and the limiting behaviours. Before we begin, one promise: every symbol below was defined in the parent, and we re-anchor each as we use it.

Quick symbol refresher (all from the parent, re-stated so line one is readable):

Definition The cast of characters

Q, QB — the two internal storage nodes. They always sit at opposite voltages: if Q is HIGH (near the supply), QB is LOW (near ground), and vice-versa. Together they store one bit.
Inverter A / Inverter B — the two CMOS inverters in the loop. Inverter A = PMOS PL + NMOS NL; its output is node Q, and its input is node QB. Inverter B = PMOS PR + NMOS NR; its output is node QB, and its input is node Q. "Cross-coupled" = A's output Q feeds B's input, and B's output QB feeds A's input.
$V_{D D}$ — the supply voltage, the "HIGH" rail. We use $V_{D D} = 1.0 V$ throughout.
$V_{M}$ (trip point / switching threshold) — the single input voltage at which an inverter's output is poised to flip: below $V_{M}$ the output snaps HIGH, above $V_{M}$ it snaps LOW. It is the "tipping point" of the see-saw. For a symmetric CMOS inverter it sits near the middle of the swing, so with $V_{D D} = 1.0 V$ we take $V_{M} \approx 0.5 V$ for both A and B (they are built identically, so they share the same tipping point). See SNM for why this midpoint matters.
WL (word line) — the wire that opens the two door transistors. WL=1 → doors open.
BL, BLB (bit lines) — the two external wires we read from / drive into. BLB is "BL-bar", the complement partner.
AL, AR — the two access (door) transistors. AL connects Q↔BL; AR connects QB↔BLB.
NL, NR — the two pull-down NMOS (yank a node toward ground = 0).
PL, PR — the two pull-up PMOS (yank a node toward $V_{D D}$ = 1).
$W / L$ — a transistor's width over length. Bigger $W / L$ = wider channel = stronger = more current = "wins" a tug-of-war. Think of it as the transistor's muscle rating.
$C R$ cell ratio $= \frac{( W / L ) _{N L}}{( W / L ) _{A L}}$ — how much stronger the pull-down is than the door. Guards read (want it ≥ ~1.2).
$P R$ pull-up ratio $= \frac{( W / L ) _{P L}}{( W / L ) _{A L}}$ — how much stronger the pull-up is than the door. Guards write (want it ≤ ~1.8).

The scenario matrix

Every question about a single 6T cell falls into one of these boxes. Our examples below are labelled by which box they hit, and together they fill the whole grid.

#	Case class	What varies	Example
A	Hold, stored `1` vs stored `0`	which node is high	Ex 1
B	Read a stored `1`	high node → which bit line droops	Ex 2
C	Read a stored `0`	the other bit line droops	Ex 3
D	Write flipping `1→0`	sign of the change on `Q`	Ex 4
E	Write flipping `0→1`	opposite sign, symmetry check	Ex 5
F	Degenerate: write fails (PR too big)	pull-up too strong	Ex 6
G	Degenerate: read flips the cell (CR too small)	pull-down too weak	Ex 7
H	Limiting/word problem — timing & $Δ V$ growth	how big must $Δ V$ get	Ex 8
I	Exam twist — both ratios at once, find safe $(W / L)$	sizing under two constraints	Ex 9

The two axes of the whole grid are: which value is stored (the "sign", 0 vs 1) and which operation (hold / read / write / failure / limit). We visit every cell.

The figure below draws this same table as a grid: the horizontal axis is the operation, the vertical axis is the stored value, and each amber label marks which worked example fills that cell. Use it as a map — every box has an example, so no scenario is left uncovered.

Figure — SRAM 6T cell structure and operation

Worked examples

Case A — Hold, both stored values

Worked example

Ex 1 (Case A). A cell has $V_{D D} = 1.0 V$ . WL=0. First it stores Q=1; later someone writes it so Q=0. In each case, give $(V_{Q}, V_{QB})$ and state the leakage behaviour.

Forecast: guess — with the doors shut, do the node voltages drift over time or stay pinned?

Stored 1: $V_{Q} = V_{D D} = 1.0 V$ , $V_{QB} = 0 V$ . Why this step? By definition the two nodes sit at opposite rails; Q=1 means Q is the high one.
Stored 0: $V_{Q} = 0 V$ , $V_{QB} = V_{D D} = 1.0 V$ . Why this step? Symmetric to step 1 — the see-saw simply tilted the other way.
Leakage: any tiny charge that leaks off the high node is instantly refilled by that node's ON pull-up PMOS; any charge leaking onto the low node is drained by its ON pull-down NMOS. Why this step? The feedback loop is always conducting while powered, so it actively corrects leakage — this is the whole meaning of "static".

Verify: the two node voltages must sum to $V_{D D}$ in an ideal cell: $1.0 + 0 = 1.0 V$ ✓, and $0 + 1.0 = 1.0 V$ ✓. No refresh clock appears anywhere — correct for SRAM (unlike DRAM, whose capacitor would need refreshing).

Cases B & C — Read a `1`, then read a `0`

Worked example

Ex 2 (Case B — read a stored 1). $V_{D D} = 1.0 V$ . Both bit lines precharged to $1.0 V$ . Cell holds Q=1, QB=0. The bit line capacitance is $C_{B L} = 2 fF$ , the discharge branch sinks $I = 20 μ A$ , and the sense amplifier fires once $Δ V = ∣ V_{B L} - V_{B L B} ∣ = 100 mV$ . How long until it fires, and which value is read?

Forecast: which bit line droops — the one on the 1 node or the 0 node?

Assert WL=1, opening AL and AR. Why this step? Only with the doors open can a node touch its bit line (WL/BL addressing).
Find the discharge path. QB=0 is the low node; through AR it connects BLB to a path to ground (via NR). So BLB discharges; BL (touching the high Q) has no sink, stays high. Why this step? Current only flows where there is a path to ground — only the 0-storing node offers one.
Time to build $Δ V$ : a constant current draining a capacitor gives $Δ V = \frac{I t}{C _{B L}}$ , so $t = \frac{C _{B L} Δ V}{I} = \frac{( 2 \times 1 0 ^{- 15} ) ( 0.1 )}{20 \times 1 0 ^{- 6}} = 1 0^{- 11} s = 10 ps$ . Why this step? $Q = C V \Rightarrow Δ V = Δ Q / C = I t / C$ ; solving for $t$ tells us the sensing delay.
Result: $V_{B L} > V_{B L B}$ , so $Δ V = V_{B L} - V_{B L B} > 0$ → sense amp reports 1. Why this step? Differential sensing maps "BL higher than BLB" to logic 1.

Verify: units — $\frac{F \cdot V}{A} = \frac{C / V \cdot V}{C / s} = s$ ✓. Numeric: $t = 10 ps$ . Sanity: 10 ps is a plausible read time, and the un-drooped line pairs with the high node — reading a 1 should leave BL high, which it does ✓.

The figure below plots both bit lines during this read: the cyan line holds at $V_{D D}$ (its node is high, no discharge path), while the amber line droops linearly as the 0 node sinks current. The white dashed marker shows the instant the differential $Δ V$ reaches 100 mV at $t = 10 ps$ — the moment the sense amp fires.

Worked example

Ex 3 (Case C — read a stored 0). Same cell, same numbers, but now it holds Q=0, QB=1. Which line droops, and what is read?

Forecast: mirror of Ex 2 — predict before reading on.

Assert WL=1. Why? Same door-opening reason as before.
Now Q=0 is the low node → through AL, BL discharges (path via NL); BLB stays high. Why this step? The discharge path swapped sides because the stored value swapped.
Same current and capacitance → same $t = \frac{( 2 \times 1 0 ^{- 15} ) ( 0.1 )}{20 \times 1 0 ^{- 6}} = 10 ps$ . Why this step? Geometry is symmetric; only the sign of $Δ V$ changes, not its magnitude.
Now $Δ V = V_{B L} - V_{B L B} = - 100 mV < 0$ → sense amp reports 0. Why this step? Negative differential = "BLB higher" = logic 0.

Verify: $∣Δ V ∣$ identical to Ex 2 (100 mV) but opposite sign — this ±symmetry is the hallmark of a balanced cell. $t = 10 ps$ again ✓. Cases B and C together cover both read polarities.

Cases D & E — Write both directions

Worked example

Ex 4 (Case D — write 1→0). Cell holds Q=1. We want Q=0. Set BL=0, BLB=1, then WL=1. Recall inverter B has input Q and output QB, with trip point $V_{M} = 0.5 V$ (the tipping voltage from the refresher). Does the cell flip?

Forecast: will forcing BL low actually drag Q all the way down, or stall halfway?

AL conducts, pulling Q down toward BL=0. Why this step? The open door ties the internal node to the externally-forced low line.
As $V_{Q}$ (which is inverter B's input) falls past $V_{M} = 0.5 V$ , inverter B flips its output QB HIGH. Why this step? An inverter flips its output once its input crosses the trip point $V_{M}$ — that is the definition of $V_{M}$ .
The now-HIGH QB (inverter A's input) drives inverter A to push its output Q even lower — positive feedback finishes the job. Why this step? Beyond the metastable point, loop gain > 1: the cell completes the flip itself.
Final: $V_{Q} = 0$ , $V_{QB} = 1.0 V$ . Flip succeeded.

Verify: the change on Q is $Δ V_{Q} = 0 - 1.0 = - 1.0 V$ (a negative swing, a 1→0 write). We forced BL=0 < V_M=0.5, so Q is dragged below the trip point — flip is guaranteed ✓. New state sums to $V_{D D}$ : $0 + 1.0 = 1.0$ ✓.

Worked example

Ex 5 (Case E — write 0→1, symmetry). Cell holds Q=0. We want Q=1. Set BL=1, BLB=0, then WL=1. Recall inverter A has input QB and output Q, with the same trip point $V_{M} = 0.5 V$ (both inverters are built identically). Does it flip?

Forecast: is this just Ex 4 with everything mirrored, or is there a hidden asymmetry?

Here the active door is AR, pulling QB down toward BLB=0. Why this step? To raise Q we drive its partner QB low; the write is easiest done by pulling the node that must go down, because an NMOS access transistor pulls down strongly.
As $V_{QB}$ (inverter A's input) crosses $V_{M} = 0.5 V$ downward, inverter A flips its output Q HIGH. Why this step? Same trip-point logic as Ex 4, applied to the other inverter — its input crossed $V_{M}$ .
Positive feedback drives Q to $V_{D D}$ and holds QB at 0. Why this step? The loop latches the new equilibrium.
Final: $V_{Q} = 1.0 V$ , $V_{QB} = 0$ . Flip succeeded.

Verify: $Δ V_{Q} = 1.0 - 0 = + 1.0 V$ — a positive swing, exactly the opposite sign of Ex 4. Cases D and E together cover both write directions, and the magnitudes match ( $1.0 V$ each) ✓, confirming a symmetric cell.

Cases F & G — the degenerate failures

Worked example

Ex 6 (Case F — write FAILS, PR too big). A designer sets $(W / L)_{P L} = 4$ , $(W / L)_{A L} = 1$ . Rule: write is safe when $P R \leq 1.8$ . Can we write a 0 over a stored 1?

Forecast: with such a beefy pull-up, does the door win the tug-of-war?

Compute $P R = \frac{( W / L ) _{P L}}{( W / L ) _{A L}} = \frac{4}{1} = 4$ . Why this step? $P R$ is the muscle ratio between the pull-up we must overpower and the door doing the overpowering.
Compare: $4 > 1.8$ → the PMOS PL is far stronger than access AL. Why this step? When $P R$ exceeds the safe bound, PL keeps refilling Q faster than AL can drain it.
Node Q never falls below $V_{M}$ → inverter B never flips → write fails; the old 1 survives. Why this step? No trip-point crossing means no positive-feedback flip.

Verify: $P R = 4 > 1.8$ ⇒ prediction "unwriteable". This is the why behind the parent's rule "keep the PMOS pull-up weak." $4$ is more than double the limit, so the failure is decisive ✓.

Worked example

Ex 7 (Case G — READ flips the cell, CR too small). A cell has $(W / L)_{N L} = 1$ , $(W / L)_{A L} = 2$ . Rule: read is safe when $C R \geq 1.2$ . During a read, does the cell survive?

Forecast: the precharged BL pushes charge onto the 0 node — does the pull-down hold the line?

Compute $C R = \frac{( W / L ) _{N L}}{( W / L ) _{A L}} = \frac{1}{2} = 0.5$ . Why this step? $C R$ measures whether the pull-down (defending the stored 0) can out-muscle the door that is shoving current in.
Compare: $0.5 < 1.2$ → the door AL is stronger than the pull-down NL. Why this step? With $C R$ below the bound, incoming read current raises the 0 node above the trip point.
Node Q (storing 0) is lifted past $V_{M}$ → the cell accidentally flips → read-destroy failure. Why this step? A read is only allowed to disturb the node slightly, never past the trip point.

Verify: $C R = 0.5 < 1.2$ ⇒ "read-unstable" — a real bug. This is exactly the SNM collapsing to zero during read. Contrast Ex 3 (Case C read) which used a well-sized cell and survived ✓.

Case H — limiting / word problem

Worked example

Ex 8 (Case H — how long can you wait before sensing?). During a read the bit line droops at a steady $\frac{d V}{d t}$ . With $C_{B L} = 2 fF$ and discharge current $I = 20 μ A$ , the line falls from $1.0 V$ . (a) What is the droop rate? (b) If the sense amp needs $Δ V = 150 mV$ instead of 100 mV, how long must WL stay high? (c) Limiting case: if the discharge current halved, what happens to the time?

Forecast: does halving the current double the time, or something else?

Droop rate: $\frac{d V}{d t} = \frac{I}{C _{B L}} = \frac{20 \times 1 0 ^{- 6}}{2 \times 1 0 ^{- 15}} = 1.0 \times 1 0^{10} V/s$ . Why this step? From $I = C \frac{d V}{d t}$ ; this is the speed the line falls, independent of target.
Time for 150 mV: $t = \frac{C _{B L} Δ V}{I} = \frac{( 2 \times 1 0 ^{- 15} ) ( 0.15 )}{20 \times 1 0 ^{- 6}} = 1.5 \times 1 0^{- 11} s = 15 ps$ . Why this step? Larger required $Δ V$ ⇒ proportionally longer wait.
Halved current $I \to 10 μ A$ : $t = \frac{( 2 \times 1 0 ^{- 15} ) ( 0.15 )}{10 \times 1 0 ^{- 6}} = 3.0 \times 1 0^{- 11} s = 30 ps$ . Why this step? $t \propto 1/ I$ , so halving $I$ doubles the time.

Verify: rate check $1 0^{10} V/s \times 15 ps = 1 0^{10} \times 1.5 \times 1 0^{- 11} = 0.15 V$ ✓. Limiting behaviour: weaker cell current → slower reads → this is why leakage-degraded cells fail timing ✓.

Case I — exam twist: satisfy BOTH ratios

Worked example

Ex 9 (Case I — find a safe sizing). You may choose integer widths (in units of a base $W / L = 1$ ) for the door $(W / L)_{A L}$ , pull-down $(W / L)_{N L}$ , and pull-up $(W / L)_{P L}$ . Requirements: $C R \geq 1.2$ and $P R \leq 1.8$ . Propose $(W / L)_{N L} = 2, (W / L)_{A L} = 1, (W / L)_{P L} = 1$ and check both.

Forecast: can one sizing satisfy two opposing constraints at once?

$C R = \frac{( W / L ) _{N L}}{( W / L ) _{A L}} = \frac{2}{1} = 2$ . Need $\geq 1.2$ : $2 \geq 1.2$ ✓ (read-stable). Why this step? A strong (wide) pull-down defends the stored value during read.
$P R = \frac{( W / L ) _{P L}}{( W / L ) _{A L}} = \frac{1}{1} = 1$ . Need $\leq 1.8$ : $1 \leq 1.8$ ✓ (writeable). Why this step? A weak (narrow) pull-up is easy for the door to override during write, so the cell can be flipped — exactly the write-ability condition we need.
Both pass ⇒ this cell reads without flipping (unlike Ex 7) and writes successfully (unlike Ex 6). Why this step? Threading both needles is the whole art of SRAM sizing.

Verify: $C R = 2$ and $P R = 1$ — both inside their windows. Note the door is the shared denominator: making it wider would lower $C R$ (bad) but the two winning transistors ( $N L$ strong, $P L$ weak) keep both ratios safe ✓. This is the balanced cell of the parent's Example 3.

Active recall

Recall Cover the answers and self-test

Which bit line droops when reading a stored 1? ::: BLB droops; BL stays high (positive $Δ V$ ). Which bit line droops when reading a stored 0? ::: BL droops; BLB stays high (negative $Δ V$ ). A cell has $P R = 4$ . Can you write it? ::: No — $4 > 1.8$ , the pull-up is too strong, write fails. A cell has $C R = 0.5$ . Is a read safe? ::: No — $0.5 < 1.2$ , the read disturbs the node past the trip point and flips the cell. Sensing time with $C_{B L} = 2 fF$ , $I = 20 μ A$ , $Δ V = 100 mV$ ? ::: $t = C Δ V / I = 10 ps$ . If the discharge current halves, what happens to read time? ::: It doubles, since $t \propto 1/ I$ . A safe sizing satisfying both rules? ::: $(W / L)_{N L} = 2, (W / L)_{A L} = 1, (W / L)_{P L} = 1$ gives $C R = 2, P R = 1$ . What is the trip point $V_{M}$ ? ::: The inverter's input voltage at which its output is poised to flip; ≈0.5 V for a symmetric cell at $V_{D D} = 1$ V.

See also the parent note for the bistability derivation, and CMOS Inverter for why the transfer curve is the decreasing function that makes $f \circ f$ intersect three times.