Foundations — SRAM 6T cell structure and operation

Before you can read the parent topic, you need the alphabet it is written in. This page defines every symbol and idea it silently assumes, in build-up order — from "what is a voltage" all the way to "why does gain bigger than 1 lock in a bit". A smart 12-year-old should be able to walk from line one.

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0. The very first picture: voltage as height

Everything electronic in this topic is about voltage — written $V$. Voltage is electrical height: how high a marble sits on a ramp. A high marble wants to roll down; a low marble sits still.

• $V_{DD}$ — the top of the hill, the supply voltage. This is the highest voltage in the chip, e.g. $1.0\text{ V}$. Every "high" or logic 1 means "sitting near $V_{DD}$".
• Ground (0 V) — the bottom of the hill. Every "low" or logic 0 means "sitting near $0$".

Why the topic needs this: every "high"/"low", every "logic 1"/"logic 0", and every named voltage in the parent note is really just a height on this hill. Fix the hill picture now and all later voltages become positions on it.

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1. Current — water flowing down the hill

Two facts we will lean on constantly:

• No path → no current (an OFF switch blocks the water).
• Bigger height difference or a wider pipe → more current.

Why the topic needs this: the parent's design rules all come down to tug-of-war between currents — "the currents balance", "whose pull wins". Those are statements about how much water flows down which pipe. Hold the water-flow picture and every later "current fight" becomes visible.

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2. The switch that all of this is made of: the transistor (MOSFET)

The single part SRAM is built from is a transistor — specifically a MOSFET. For this topic you only need the cartoon version: it is a voltage-controlled water valve.

There are two flavours, and the difference matters for every sentence in the parent note:

Why the topic needs this: the parent names six transistors and every name is just a flavour letter (P/N) plus a position letter. If you know N-pulls-down and P-pulls-up, you can read every transistor in the whole cell without memorising anything.

2.1 Threshold voltage $V_{tn}$ — the valve's "click" point

A MOSFET doesn't switch at exactly the middle. It needs the gate to pass a small threshold before the valve cracks open.

Why the topic needs this: the parent's read-stability argument hinges on a node voltage staying below the click point of the next valve. That click point is $V_{tn}$: if a disturbed node rises past it, the wrong valve opens and the stored bit flips. You cannot judge "did it stay safe?" without this threshold.

2.2 Width-over-length $(W/L)$ — how wide the pipe is

Why the topic needs this: every design decision in the parent is set by comparing pipe fatness. The two headline ratios you will meet in Section 6 are literally ratios of $W/L$ — "which pipe is fatter?" — so you must own $W/L$ first.

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3. The inverter — the see-saw's single arm

Stack one PMOS (pull-up) on top of one NMOS (pull-down), tie their gates together as the input, tie their drains together as the output. That is a CMOS inverter.

• Input HIGH → NMOS ON (pulls output down to 0), PMOS OFF → output = 0.
• Input LOW → PMOS ON (pulls output up to $V_{DD}$), NMOS OFF → output = 1.

Why the topic needs this: the parent's bistability derivation is entirely about composing $f$ with itself, and about $V_M$; and the "trip point" that read stability must not cross is exactly this $V_M$. You cannot follow the "why cross-couple" section without both of these.

Recall Why is the transfer curve

decreasing, not increasing? Because an inverter inverts: higher input pushes the output the other way (down). A decreasing curve is the whole point of the device. ::: A decreasing $f$ is what makes two of them, looped, compose into an increasing $f(f(\cdot ))$ — which is what gives two stable states.

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4. Cross-coupling and positive feedback — why the tilt locks

Take two inverters. Call them inverter A and inverter B. Feed inverter A's output into inverter B's input, and feed inverter B's output back into inverter A's input. That loop is cross-coupling.

Why the topic needs this: this is the beating heart of the parent's "Why cross-couple?" section — the composition $V_Q=f(f(V_Q))$, the three intersections, the stable rails, the unstable metastable point. The whole reason SRAM is static (needs no refresh) is that gain-below-1 at the rails keeps regenerating the bit. Related device: the CMOS Inverter, looped into a latch.

Now that inverters A and B are named, the parent's read rule "node Q must stay below the trip point of inverter B" reads cleanly: it means Q (driven by A) must not push B's input past B's own $V_M$, or B flips and drags the whole loop with it.

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5. The wires that talk to the cell: word line and bit lines

Storing a bit is useless if you can't reach it. Three wires do the talking. See Bit line and Word line addressing.

Why the topic needs this: every read/write step in the parent is "raise WL", "precharge BL", "force BLB=1". These three wires plus two doors are the whole interface. Now the parent's phrase "BL discharges through AL+NL" is readable: current leaves the bit line through access door AL and drains to ground through pull-down NL.

5.1 Differential voltage $\Delta V$ and precharge

Why the topic needs this: "a small differential voltage builds; a sense amplifier detects it" — that sentence assumes precharge, $\Delta V$, and its sign. Now you have all three.

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6. The two design ratios, finally readable

With everything above — $W/L$ (pipe fatness), the access transistors AL, and the inverter transistors NL, PL — the parent's headline rules decode cleanly. Both are dimensionless ratios comparing pipe fatness:

The margin of how much noise the held bit can survive before flipping has its own name: Static Noise Margin. See Static Noise Margin (SNM).

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Prerequisite map

Compare the leaky-capacitor alternative once you finish here: DRAM 1T1C cell. Back to the main topic: SRAM 6T cell.

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Equipment checklist

Hide the right side and test yourself. You are ready when every line is automatic.

• What is voltage, physically? ::: Electrical "height" on a hill; charge flows from high to low.
• What do $V_{DD}$ and ground mean as logic levels? ::: $V_{DD}$ = logic 1 (top), $0\text{ V}$ = logic 0 (bottom).
• When is current allowed to flow? ::: Only with a height difference (voltage) AND an open path.
• An NMOS turns on when its gate is ___ and pulls a node ___. ::: HIGH; DOWN toward 0.
• A PMOS turns on when its gate is ___ and pulls a node ___. ::: LOW; UP toward $V_{DD}$.
• What does "stronger transistor" mean? ::: Bigger $W/L$ = fatter pipe = more current = wins tug-of-war.
• What is $V_{tn}$? ::: The gate voltage at which an NMOS just starts to conduct (its click point).
• What does a CMOS inverter do, and is its $f$ increasing or decreasing? ::: Outputs the opposite of input; $f$ is monotonically decreasing.
• What is the trip point $V_M$? ::: Input voltage where inverter output equals input — its tipping point.
• What does cross-coupling create, and what does loop gain $>1$ cause? ::: Positive feedback; a nudge grows and runs away to a rail (metastable middle).
• Why is SRAM static (no refresh)? ::: Loop gain $<1$ at the rails constantly regenerates the bit.
• What are WL, BL, BLB? ::: Word line (doorbell), and the two bit lines (differential speaking tubes).
• What is $\Delta V$ and why precharge? ::: Precharge equalises both lines at $V_{DD}$; $\Delta V$ is the tiny sign-carrying gap the cell then opens.
• Write $CR$ and $PR$ and which operation each protects. ::: $CR=(W/L{)}_{NL}/(W/L{)}_{AL}$ protects read; $PR=(W/L{)}_{PL}/(W/L{)}_{AL}$ enables write.