SRAM 6T cell structure and operation: Question bank

Notation reminder before we start, so no symbol appears unearned:

Q, QB — the two internal storage nodes; they always sit at opposite voltages (one near $0 V$ , one near $V_{D D}$ , the supply voltage).
WL — word line, the wire that switches the two access transistors (the "doors") on/off.
BL, BLB — the two bit lines, the wires outside the cell used to read or write.
NL/NR — internal pull-down NMOS transistors (they yank a node down to $0$ ).
PL/PR-dev — internal pull-up PMOS transistors (they yank a node up to $V_{D D}$ ). We write the right pull-up device as PR-dev on this page so it never clashes with the ratio PR below.
AL/AR — access NMOS transistors (the doors between Q/QB and BL/BLB).
(W/L) — a transistor's width-over-length ratio; bigger $W / L$ = "stronger" = more current.
CR — cell ratio (a number, not a device) $= (W / L)_{N L} / (W / L)_{A L}$ , guards read stability.
PR — pull-up ratio (a number, not a device) $= (W / L)_{P L} / (W / L)_{A L}$ , guards write-ability.
≳ and ≲ — "approximately greater than or equal to" and "approximately less than or equal to." So $C R ≳ 1.2$ means "keep $C R$ at least about $1.2$ , with a little margin"; $P R ≲ 1.8$ means "keep $P R$ at most about $1.8$ ." They are soft design bounds, not exact equalities.
loop gain — how much a small voltage wobble is multiplied after going once around the two-inverter feedback loop; $> 1$ = wobble grows (unstable), $< 1$ = wobble shrinks (stable).

Before the traps, five reference figures. Refer back to them inside the answers — the pictures carry the reasoning, the words only point at them.

Fig. 1 — The 6T cell you are being quizzed on. Learn which device is which before answering.

Figure — SRAM 6T cell structure and operation

Fig. 2 — VTC composition: why there are exactly three intersections. The blue curve is one inverter, the orange is the loop composition $f \circ f$ ; where it crosses the gray identity line are the two stable rails (green) and the one unstable middle (red).

Fig. 3 — The SNM "butterfly." Two mirrored inverter curves; the largest square that fits in an "eye" is the noise margin — how much noise the cell tolerates before it flips.

Fig. 4 — Read vs. write on the bit lines (timing). Read precharges both lines high and lets the cell tug one down; write actively drives the lines to the new value.

Fig. 5 — The sense amp is itself a cross-coupled latch. It seeds on a tiny $Δ V$ and its own positive feedback slams the output to full swing.

True or false — justify

Each line: a claim, then :::, then the verdict with the reason.

SRAM is non-volatile because it needs no refresh.

False — no-refresh makes it static, not non-volatile; cut the power and both nodes collapse, so the bit is still lost. Volatile ≠ dynamic.

All six transistors in a 6T cell store the bit.

False — only the 4 cross-coupled inverter transistors (NL,PL,NR,PR-dev) hold state (the boxed core in Fig. 1); AL and AR are just switches to the bit lines.

The cell holds its value because the access transistors keep it connected to the bit lines.

False — it's the opposite: in HOLD WL=0 turns the access transistors off, isolating the nodes; the internal feedback loop is what retains the bit.

Making every transistor as wide as possible gives the best cell.

False — a wide (strong) PMOS pull-up makes PR too large and the cell becomes unwriteable; sizing is a compromise, not a maximisation.

During a read, the bit line writes its precharged value into the cell.

False — that's the danger we design against:

C R > 1

makes the internal pull-down NL stronger than access AL, so node Q barely rises (see the small bump on BL in Fig. 4) and never crosses the trip point.

A larger cell ratio CR improves both read stability and write-ability.

False — larger CR helps read stability but a strong pull-down actually makes writing the opposite node slightly harder; read and write pull sizing in opposite directions.

The metastable point is a valid third state you could store a bit in.

False — it is unstable: loop gain there is

> 1

, so any noise is amplified and drives the cell to a rail (the red middle crossing in Fig. 2). You cannot rest there.

Both stable states have loop-gain magnitude greater than 1.

False — at the two stable rails the loop gain magnitude is

< 1

(nudges die out); only the middle metastable point has gain

> 1

. Compare the slopes at the green vs. red dots in Fig. 2.

A single inverter can store one bit on its own.

False — one inverter just computes high→low; you need two in a loop so the output feeds back and creates the positive feedback that locks a state.

Precharging both bit lines to

V_{D D}

before a read is optional.

False — differential sensing needs a common starting point so the Sense Amplifier can detect a small

Δ V

between BL and BLB; without precharge there's no clean reference.

Reducing

(W / L)_{P L}

(weaker pull-up) always helps the cell.

False (as a blanket rule) — it helps write (smaller PR) but too weak a pull-up shrinks the butterfly eye in Fig. 3, hurting Static Noise Margin (SNM); it's a trade, not a free win.

If Q=0, then QB must be 1.

True — the cross-coupling forces the nodes to opposite rails; a stable state always has them complementary (the two green corners in Fig. 3).

Spot the error

Each line quotes a plausible-sounding statement; the reveal names the specific flaw.

"To read, we drive BL low and raise WL; the sense amp then reads the low line."

Error — driving a bit line low is a write, not a read (contrast the two panels of Fig. 4). For read you precharge both lines high and let the cell's 0-node discharge one of them.

"CR = (W/L)_{AL}/(W/L)_{NL} should be at least ~1.5."

Error — the ratio is inverted.

C R = (W / L)_{N L} / (W / L)_{A L}

; the pull-down must be the bigger (stronger) one.

"For a good write we want PR large so the PMOS holds the node firmly."

Error — a firm-holding PMOS resists flipping. Write needs PR small (weak pull-up) so access AL can override it.

"Since the see-saw always balances at the middle, that middle is where the cell rests."

Error — a real see-saw balances there, but this one has gain

> 1

at the middle, so it refuses to balance and topples to a side (red dot, Fig. 2).

"Read disturb flips the cell when the access transistor is weaker than the pull-down."

Error — reversed. Flipping is a risk when access is too strong relative to the pull-down (i.e. CR too small); a strong pull-down protects the cell.

"HOLD works because the bit lines constantly refill the storage nodes."

Error — in HOLD the bit lines are disconnected (WL=0); the internal feedback loop refills leakage, not the bit lines.

"6T SRAM needs a refresh cycle, just less often than DRAM."

Error — SRAM needs no refresh at all; only DRAM 1T1C cell's passive capacitor leaks and requires periodic refresh.

"During write, only the cell's own transistors decide the final state."

Error — the external bit-line drive kicks it past the metastable point, then the internal positive feedback finishes the flip; both matter.

Why questions

Each line: a "why", then the reasoning.

Why do we make the pull-down NMOS stronger than the access NMOS?

So that during read the precharged bit line, pushing current into the 0-node, can't lift that node above inverter B's trip point — the strong pull-down keeps Q low (the tiny BL dip in Fig. 4) and prevents an accidental flip.

Why do we deliberately keep the PMOS pull-up weak?

So that during write the access transistor can win the fight and yank the held-high node down; a strong pull-up would make the cell unwriteable.

Why does the composition of two decreasing inverter curves give bistability?

Two decreasing functions compose to an increasing one, and that increasing orange curve crossing the gray identity line intersects three times (Fig. 2) — two stable rails plus one unstable middle — which is exactly two storable states. See Positive Feedback and Latches.

Why use two complementary bit lines instead of one?

A differential pair lets the sense amp compare BL against BLB and act on a tiny

\sim 100 mV

difference (Fig. 4), which is faster and far more noise-immune than judging one line against a fixed threshold.

Why is a small

Δ V

enough to read the cell?

The Sense Amplifier is itself a positive-feedback latch (Fig. 5); it amplifies the tiny differential to full swing, so the cell only has to start separating the lines, not fully discharge one.

Why does write only need to push the node "past the metastable point," not all the way?

Beyond that point the loop gain is

> 1

, so the cell's own positive feedback regenerates and completes the flip; the external drive just gets it over the hump (the red middle of Fig. 2).

Why do read stability and write-ability conflict?

Read wants a strong pull-down and stubborn cell (hard to disturb); write wants an easy-to-flip cell (weak pull-up). Stubborn-yet-easy-to-flip are opposites, so sizing threads a needle.

Why does the cell not lose its bit to leakage the way DRAM does?

DRAM stores charge passively on a capacitor that slowly bleeds away; SRAM's node is actively driven by an always-on transistor in the feedback loop, so leakage is continuously replenished.

Why is WL asserted for both read and write but the bit-line handling differs?

WL just opens the doors; what happens depends on whether the bit lines are left floating-high to be sensed (read) or actively driven to a new value (write) — the two panels of Fig. 4.

Why is a small SNM square in the butterfly a warning sign?

A small square (Fig. 3) means only a little noise separates the state from the metastable crossing, so the cell flips easily — it is the geometric measure of how safe the stored bit is.

Edge cases

Each line: a boundary/degenerate scenario, then what actually happens.

What if Q and QB are momentarily equal (e.g. right after power-up)?

They sit at the metastable point (red dot, Fig. 2); the smallest thermal noise, amplified by gain

> 1

, tips the cell to one rail — the final value is effectively random unless a reset forces it.

What if CR is set exactly at the design boundary, say

C R = 1

Access and pull-down are equally strong, so during read node Q can rise near the trip point (imagine the BL bump in Fig. 4 growing until it reaches the switching level); the cell is marginal and may flip — hence the rule

C R ≳ 1.2

What if PR is exactly at its upper bound, e.g.

P R = 1.8

The access transistor barely overpowers the pull-up; writes succeed only marginally and may fail across process/voltage/temperature spread — designers keep a margin below that.

What happens if you try to write a value equal to what's already stored?

Nothing visible changes — the cell is already in that stable state (a green corner of Fig. 3); the operation is harmless but wasteful (a "write same").

What if the word line is asserted but both bit lines are left precharged high during a write?

No write happens — with no low bit line there's no pull to a new value; it degenerates into a read-like access (the read panel of Fig. 4).

What if leakage on the 1-node were somehow faster than the pull-up could refill?

The node would droop, shrinking the butterfly eye in Fig. 3 and collapsing the Static Noise Margin (SNM) until a flip — which is why the pull-up must never be too weak; write-ease and hold-robustness both constrain it.

What if WL glitches high momentarily during a hold?

The doors briefly open and the precharged bit lines can disturb the nodes (a short spike like the start of the read panel in Fig. 4); if CR is adequate the cell survives, otherwise a spurious read-upset can flip it.

Active recall

Recall One-line trap summary (hide and recite)

Static ≠ non-volatile → static means no refresh, still lost on power-off.
6 transistors, but only 4 store the bit (Fig. 1 core).
HOLD isolates the nodes; feedback (not bit lines) retains data.
Read wants strong pull-down ( $C R ≳ 1.2$ ); write wants weak pull-up ( $P R ≲ 1.8$ ) — opposite pulls.
Metastable middle has loop gain $> 1$ (unstable); rails have gain $< 1$ (stable) — Fig. 2.
Precharge both lines so the sense amp reads a small differential $Δ V$ — Figs. 4 & 5.
Small butterfly square = small SNM = flips easily — Fig. 3.