SRAM 6T cell structure and operation: Visual walkthrough

We are going to derive the parent note's central result — bistability — using only pictures. Every symbol is earned before it's used.

Step 1 — What an inverter does (the one curve everything rests on)

WHAT. An inverter is a little circuit with one wire in and one wire out. Its rule: high voltage in gives low voltage out, and low in gives high out. We measure voltage as a number between $0$ and a top value we call $V_{D D}$ (think "full battery", e.g. $1.0 V$ ).

We write this rule as a function: $V_{o u t} = f (V_{in})$

$V_{in}$ ::: the voltage we push into the inverter (the cause).
$V_{o u t}$ ::: the voltage that comes out (the effect).
$f$ ::: the inverter's personal rule — the machine that turns one into the other.

WHY a function and not just "0 and 1"? Because in between $0$ and $V_{D D}$ the output changes smoothly. That smooth in-between is exactly where the interesting behaviour lives, and we can't see it if we only think in perfect 0s and 1s.

PICTURE. The curve slopes downward: as you slide $V_{in}$ right (bigger), $V_{o u t}$ slides down. In the middle there's a steep cliff — a tiny change in input flips the output hard.

Figure — SRAM 6T cell structure and operation

Step 2 — Wiring two inverters nose-to-tail

WHAT. Take two identical inverters, call them A and B. Feed A's output into B's input, and feed B's output back into A's input. That loop is called cross-coupling. Name the two loop wires:

$V_{Q}$ ::: the voltage on node Q (output of inverter A).
$V_{QB}$ ::: the voltage on node QB ("Q-bar", output of inverter B).

The two wiring rules, side by side: $V_{QB} = f (V_{Q}) and V_{Q} = f (V_{QB})$

The left equation: B looks at Q and produces QB.
The right equation: A looks at QB and produces Q.

WHY loop them? One inverter alone just flips a value and forgets it. Looped, each one is watching the other and pushing back — that mutual pushing is what we'll show creates memory.

PICTURE. A ring: $Q \to$ B $\to QB \to$ A $\to Q$ . The signal chases its own tail.

This "output feeds back to affect the input" is exactly positive feedback — hold that thought.

Step 3 — Collapsing the loop into ONE equation

WHAT. We have two equations but they share the same two unknowns. Substitute the right one into the left one to eliminate $V_{QB}$ : $V_{Q} = f (f (V_{Q}))$

Inner $f$ ::: inverter A turning $V_{QB}$ into... wait — read it as: start with $V_{Q}$ , apply $f$ once (that's inverter B making QB), apply $f$ again (inverter A making Q). We must come back to the same $V_{Q}$ we started with.
$f (f (\cdot))$ ::: the two inverters chained. We call this the round-trip rule.

WHY substitute? A stable stored state is one that survives a full trip around the loop unchanged. That "unchanged after a round trip" is precisely the equation $V_{Q} = f (f (V_{Q}))$ . Solving it finds every state the cell can rest in.

Key fact about direction. Down composed with down is up: a decreasing function fed into a decreasing function increases. (Slide input right → first $f$ goes down → feeding a lower value into the second $f$ makes it go up.) So $f (f (V_{Q}))$ is monotonically increasing.

PICTURE. The single downward inverter curve, and beside it the gentle upward round-trip curve $g (V_{Q}) = f (f (V_{Q}))$ .

Step 4 — Finding the resting states graphically

WHAT. We need the voltages where $V_{Q} = f (f (V_{Q}))$ . On a graph, "output equals input" is the 45° diagonal line $y = x$ . So we draw:

the upward round-trip curve $g (V_{Q})$ , and
the straight diagonal $y = V_{Q}$ ,

and look for where they cross. Each crossing is a solution — a state that survives the round trip.

WHY the diagonal? The diagonal is the set of all points where "what came out" equals "what went in". Crossings of any curve with this diagonal are its fixed points — values the system doesn't want to move away from (or toward, we'll check next).

PICTURE. They cross three times: near the bottom-left ( $V_{Q} \approx 0$ ), near the top-right ( $V_{Q} \approx V_{D D}$ ), and once in the dead centre.

Step 5 — Which crossings are STABLE? (the slope test)

WHAT. Not all three fixed points are equal. The difference is the steepness of the round-trip curve where it crosses the diagonal. That steepness is the loop gain, written $∣ A_{l oo p} ∣$ — how much a small nudge gets multiplied each trip around the loop.

$∣ A_{l oo p} ∣ = slope of g at the crossing$

slope less than 1 (curve flatter than the diagonal) → a nudge shrinks each trip → the state pulls itself back = stable.
slope greater than 1 (curve steeper than the diagonal) → a nudge grows each trip → the state runs away = unstable.

WHY does slope decide? Push $V_{Q}$ a hair off a fixed point. One round trip multiplies that hair by the local slope. If slope $< 1$ the hair fades to nothing (snaps back); if slope $> 1$ the hair blows up (flees to a rail). This is the whole see-saw intuition made exact.

PICTURE. At the two end crossings the curve is flat (slope $< 1$ , green = stable). At the middle crossing it's steep (slope $> 1$ , pink = unstable). Little arrows show nudges dying at the ends and exploding in the middle.

Step 6 — Edge case: what if the two inverters aren't identical?

WHAT. Real transistors never match exactly. Suppose inverter B is slightly stronger, so its curve shifts a bit. Do we still get bistability?

WHY check this? A derivation that only works for perfect symmetry is useless in silicon. We must cover the skewed case.

PICTURE. The round-trip curve tilts, so the middle crossing $V_{M}$ slides off-centre — but the two flat end crossings survive. As long as the mismatch isn't huge, we still have two stable states. Push mismatch too far and the curve stops crossing the diagonal three times: it flattens into a single crossing — the cell loses one state and can no longer store both values.

Step 7 — Edge case: the metastable middle, zero and full rails

WHAT. Two degenerate scenarios worth drawing:

Perfectly at $V_{M}$ ( $V_{Q} = V_{QB}$ , loop gain $> 1$ ): the ideal see-saw balanced flat. Slope $> 1$ guarantees any noise, even a single electron's worth, gets amplified and ejects it to a rail. It never lingers.
At a rail ( $V_{Q} \approx 0$ or $V_{Q} \approx V_{D D}$ ): here slope $\approx 0$ . A nudge is crushed almost instantly. Leakage that tries to droop the node gets refilled by the feedback — this is the static, refresh-free hold the parent note promised, and the opposite of the leaky DRAM 1T1C cell.

PICTURE. A timeline: a dot started exactly at $V_{M}$ visibly wobbling, then avalanching to a rail; a dot started at a rail barely twitching under noise and returning.

The one-picture summary

WHAT. One frame stitches the whole argument: the downward inverter curve $\to$ its upward round-trip $g$ $\to$ three crossings with the diagonal $\to$ two green stable rails (a 0 and a 1) and one pink forbidden middle.

WHY it's the payoff. Two inverters + a loop = positive feedback with gain $> 1$ in the middle = exactly two locked-in states = 1 bit that holds itself. That is the parent note's central claim, now seen, not just told. Each inverter is a CMOS Inverter; the loop is a latch; the two stable lobes are what a Sense Amplifier later reads through the bit lines.

Recall Feynman retelling — the whole walkthrough in plain words

One inverter is a contrarian: tell it "high", it says "low". (Step 1) Wire two contrarians in a circle, each listening to the other. (Step 2) Ask: what voltage survives a full lap around the circle unchanged? That's $V_{Q} = f (f (V_{Q}))$ . (Step 3) Draw the lap-curve against the 45° "unchanged" line — they touch in three spots. (Step 4) Where the lap-curve is flat, a nudge dies and the spot is a safe resting place (that's a stored 0 and a stored 1). Where it's steep, a nudge explodes — that middle spot can't be held. (Step 5) Even mismatched inverters keep the two safe spots, up to a limit measured by the noise-margin square. (Step 6) The middle is a pencil on its tip (always topples); the ends are marbles in bowls (always return, and the feedback quietly refills leakage — no refresh needed). (Step 7) So: two contrarians in a loop = two locked states = one bit that guards itself. (Summary)

Recall Quick self-test

Why does composing two decreasing curves give an increasing one? ::: down-into-down flips twice, so overall it rises. What does a crossing with the $y = x$ diagonal mean physically? ::: a voltage that returns to itself after one loop trip — a resting state. Slope $< 1$ at a crossing means? ::: stable — nudges shrink and the state snaps back. Slope $> 1$ at a crossing means? ::: unstable (metastable) — nudges grow and it flees to a rail. Why can't the cell store the middle value $V_{M}$ ? ::: loop gain there is $> 1$ , so any noise is amplified and ejects it to a rail. What survives even when the two inverters are mismatched? ::: the two flat stable crossings, until mismatch exceeds the noise margin.