SRAM 6T cell structure and operation: Exercises — Hardware deep dive

Before we climb, one reminder of the symbols we will reuse (all defined in SRAM 6T cell structure and operation):

Definition Symbols you will need on every rung

$Q$ , $QB$ — the two storage nodes (the two ends of the see-saw). They always sit at opposite voltages: one near $0$ , one near $V_{D D}$ .
$V_{D D}$ — the supply voltage (the "top rail", the highest voltage in the circuit).
$B L$ , $B L B$ — the two bit lines: long metal wires that carry data in and out. See Bit line and Word line addressing.
$W L$ — the word line: the wire that opens the two access "doors".
$N L, N R$ — the two pull-down NMOS transistors (they yank a node toward $0$ ).
$P L, P R$ — the two pull-up PMOS transistors (they lift a node toward $V_{D D}$ ). Note: the device PMOS $P L$ is a transistor; the ratio written $PUR$ below is a number. Keep them apart — same two letters would collide, so the ratio gets its own name.
$A L, A R$ — the two access transistors (the doors).
$(W / L)$ — a transistor's width-to-length ratio. Bigger $W / L$ = a wider channel = it can pass more current = it is "stronger". Think of it as the diameter of a water pipe.
$I_{x}$ — the current flowing through transistor $x$ (electric charge per second passing through that device). E.g. $I_{A L}$ is the current through access transistor $A L$ . Larger $W / L$ ⇒ larger $I_{x}$ .
Trip point $V_{t r i p}$ — the input voltage at which a CMOS inverter switches over (its output crosses the halfway mark from high to low). If a node's voltage is pushed past the trip point of the inverter it drives, that inverter starts flipping — which is how a stored bit gets destroyed. Its value depends on the transistor sizes; a common figure is around $0.4 V_{D D}$ .
$C R = \frac{( W / L ) _{N L}}{( W / L ) _{A L}}$ — the cell ratio (guards READ stability).
$PUR = \frac{( W / L ) _{P L}}{( W / L ) _{A L}}$ — the pull-up ratio (guards WRITE ability). We write it $PUR$ , not $P R$ , so it can never be confused with the PMOS device $P R$ .

Definition Two ideas Level 3 will lean on — build them now

The inverter transfer function $f$ . A single CMOS inverter takes an input voltage and produces an output voltage. Call this rule $f$ : if the input is $V_{in}$ , the output is $V_{o u t} = f (V_{in})$ . Two facts about $f$ are all we need:

$f$ is decreasing — a high input gives a low output and vice versa (that's what "invert" means).
$f$ maps the range $0 \dots V_{D D}$ back into $0 \dots V_{D D}$ (it's an S-shaped curve: flat–steep–flat).

In the cell, node $Q$ drives inverter B ( $V_{QB} = f (V_{Q})$ ) and node $QB$ drives inverter A ( $V_{Q} = f (V_{QB})$ ). Chaining them gives $V_{Q} = f (f (V_{Q}))$ ; we name that composed rule $g (V_{Q}) = f (f (V_{Q}))$ . Because a decreasing function of a decreasing function is increasing, $g$ is an increasing S-curve — the one drawn in the Level-3 figure.

Loop gain = the slope of $g$ . "Loop gain" is just a name for how much a tiny voltage wiggle is multiplied after it travels once around the feedback loop. If you nudge $V_{Q}$ by a small amount $δ$ , the output of $g$ changes by (slope of $g$ ) $\times δ$ . So the slope of $g$ at a point literally is the loop gain there. Slope $< 1$ ⇒ the wiggle comes back smaller (it dies); slope $> 1$ ⇒ it comes back bigger (it grows). Keep this equation in mind: slope of $g$ = loop gain.

Level 1 — Recognition

Exercise 1.1

How many transistors store the actual bit in a 6T cell, and how many are only switches? Name each group.

Recall Solution

Storage: 4 transistors — they form the two cross-coupled inverters: $P L, N L$ (making node $Q$ ) and $P R, N R$ (making node $QB$ ).
Switches: 2 transistors — the access transistors $A L$ and $A R$ . They store nothing; they only connect $Q \leftrightarrow B L$ and $QB \leftrightarrow B L B$ when $W L = 1$ .
$4 + 2 = 6$ , hence "6T".

Exercise 1.2

During HOLD, what is the value of $W L$ , and what does that value do to $A L$ and $A R$ ?

Recall Solution

$W L = 0$ . A word line of $0$ turns both access transistors OFF. The storage nodes are then isolated from the bit lines, and the feedback loop keeps $Q$ and $QB$ pinned at opposite rails — no refresh needed. That is exactly why SRAM is called static.

Exercise 1.3

Which single formula tells you whether a cell can be read without being accidentally flipped: $C R$ or $PUR$ ?

Recall Solution

The cell ratio $C R = \frac{( W / L ) _{N L}}{( W / L ) _{A L}}$ . It compares the internal pull-down strength against the access strength; a large $C R$ means the pull-down "wins" and the stored $0$ node is not disturbed during read. ( $PUR$ is for write, not read.)

Level 2 — Application

Exercise 2.1

A cell holds $Q = 0, QB = 1$ . Both bit lines are precharged to $V_{D D} = 1.0 V$ , then $W L = 1$ . Which bit line discharges, and roughly what differential $Δ V = V_{B L} - V_{B L B}$ sign results?

Recall Solution

Node $Q = 0$ offers a path to ground through $A L$ then $N L$ . So $B L$ discharges (drops below $V_{D D}$ ). Node $QB = 1$ has no sink, so $B L B$ stays $\approx V_{D D}$ .
$Δ V = V_{B L} - V_{B L B} < 0$ (BL is now lower). A Sense Amplifier detects this negative $Δ V$ and reports a stored 0.
Only a small $Δ V \approx 100 mV$ is needed, which is why sensing is fast.

Exercise 2.2

You want to write a 1 into a cell currently holding $Q = 0$ . State the values you drive on $B L$ , $B L B$ , and $W L$ , and which internal transistor $A R$ must overpower.

Recall Solution

To make $Q = 1$ we force the other node $QB = 0$ through $B L B$ :

Drive $B L = 1$ (= $V_{D D}$ ), $B L B = 0$ , then raise $W L = 1$ .
Access $A R$ ties $QB$ toward $B L B = 0$ . It must overpower $P R$ (the PMOS device that is currently holding $QB$ high). Once $QB$ crosses the trip point, positive feedback flips $Q$ up to $1$ .
Winning over the pull-up is governed by the pull-up ratio (here for the right side) $PUR = \frac{( W / L ) _{P R}}{( W / L ) _{A R}}$ being small enough.

Exercise 2.3

Given $(W / L)_{N L} = 3, (W / L)_{A L} = 1.5, (W / L)_{P L} = 1$ . Compute $C R$ and $PUR$ . Is the cell read-stable ( $C R \geq 1.2$ ) and writeable ( $PUR \leq 1.8$ )?

Recall Solution

$C R = \frac{3}{1.5} = 2.0 \geq 1.2 ✓ PUR = \frac{1}{1.5} \approx 0.67 \leq 1.8 ✓$ Both rules pass → the cell is read-stable and writeable. Strong pull-down ( $C R = 2$ ) resists read disturb; weak pull-up ( $PUR \approx 0.67$ ) is easily overridden during write.

Level 3 — Analysis

Exercise 3.1

Using $f$ and $g (V_{Q}) = f (f (V_{Q}))$ as defined in the opening callouts, the curve $g$ crosses the identity line $y = V_{Q}$ three times. In the figure below these crossings are labelled A, B, C. Classify each as stable or unstable, and justify using the slope of $g$ (which, as we established, equals the loop gain).

Figure — SRAM 6T cell structure and operation

Recall Solution

How to read the figure. The horizontal axis is $V_{Q}$ (the voltage at node $Q$ , from $0$ to $V_{D D}$ ). The violet S-curve is $g (V_{Q}) = f (f (V_{Q}))$ — one trip around the feedback loop. The dashed orange line is the identity $y = V_{Q}$ ; wherever the violet curve meets it, the loop is in equilibrium (a voltage that maps back to itself). Those three meeting points are the dots A, B, C.

Now classify each using the rule slope of $g$ = loop gain:

Crossing A (near $V_{Q} \approx 0$ ): the violet curve is nearly flat there → slope $< 1$ → loop gain $< 1$ . A small nudge comes back smaller and dies → stable (this is the $Q = 0$ state).
Crossing C (near $V_{Q} \approx V_{D D}$ ): again flat → slope $< 1$ → gain $< 1$ → stable (the $Q = V_{D D}$ state).
Crossing B (the middle, $V_{Q} = V_{QB} = V_{M}$ ): the curve is steep → slope $> 1$ → loop gain $> 1$ . Any noise is amplified each trip around the loop and grows → unstable (metastable). Gain $< 1$ locks the state in; gain $> 1$ is the see-saw refusing to balance on its edge. See Positive Feedback and Latches.

Exercise 3.2

During a read of a stored $0$ , the precharged $B L$ pushes current into node $Q$ , raising it to a small voltage $V_{r e a d}$ . Explain the current-balance condition that sets $V_{r e a d}$ , and why $C R > 1$ keeps $V_{r e a d}$ below the inverter trip point.

Recall Solution

Node $Q$ is being charged by current through the access transistor $A L$ (from high $B L$ ) and discharged by the pull-down $N L$ (toward ground). Writing $I_{A L}$ for the current through $A L$ and $I_{N L}$ for the current through $N L$ (charge-per-second through each device), $Q$ settles where these two currents are equal: $I_{A L} = I_{N L} \Rightarrow V_{r e a d} fixed at the balance point.$ Because current scales with $W / L$ , a stronger $N L$ (larger $C R$ ) sinks the injected charge more aggressively, so the balance point $V_{r e a d}$ stays low — below the trip voltage $V_{t r i p}$ of inverter B. If $V_{r e a d}$ ever exceeded $V_{t r i p}$ , inverter B would start flipping and the cell would lose its bit. Hence the rule $C R ≳ 1.2$ : pull-down must out-muscle access.

Exercise 3.3

A designer keeps $A L$ fixed and doubles $(W / L)_{N L}$ . What happens to read stability and to the cell read speed (how fast $B L$ discharges)? Are they helped or hurt?

Recall Solution

Read stability: improved. $C R$ doubles, so $V_{r e a d}$ drops further below the trip point — the cell is harder to disturb.
Read speed: improved too. The discharge path $B L \to A L \to N L \to$ ground carries more current when $N L$ is wider, so $Δ V$ builds faster.
The catch: a wider $N L$ costs area and adds capacitance, and the read path is limited by the series combination of $A L$ and $N L$ — once $A L$ is the bottleneck, widening $N L$ further gives diminishing speed returns. Stability keeps improving, speed plateaus.

Level 4 — Synthesis

Exercise 4.1

Design a cell. You must satisfy both $C R \geq 1.5$ and $PUR \leq 1.5$ , using integer or half-integer $W / L$ values, with $(W / L)_{A L} = (W / L)_{A R} = 1$ (access fixed by layout). Choose $(W / L)_{N L}$ and $(W / L)_{P L}$ and verify both rules.

Recall Solution

With access $= 1$ :

\mathrm{PUR}=\frac{(W/L)_{PL}}{1}\le 1.5 \Rightarrow (W/L)_{PL}\le 1.5.$$ A clean choice: $(W/L)_{NL}=2$, $(W/L)_{PL}=1$. - $CR=2/1=2\ge1.5\ \checkmark$ - $\mathrm{PUR}=1/1=1\le1.5\ \checkmark$ This encodes the whole design philosophy: **strong pull-down, weak pull-up, unit access.**

Exercise 4.2

Explain why read and write pull transistor sizing in opposite directions, and what property of the cell would break if you tried to satisfy write by making the PMOS stronger instead of the access stronger.

Recall Solution

Read wants the internal pull-down to dominate the access door → big $C R$ → strong $N L$ .
Write wants the access door to dominate the internal pull-up → small $PUR$ → weak $P L$ .
So $N L$ should be big and $P L$ should be small: opposite pulls on the two node-forming NMOS/PMOS.
If you tried to help write by making the PMOS stronger, you'd increase $PUR$ , which makes the node harder to pull low — write gets worse, not better. Writeability is improved only by weakening $P L$ or strengthening the access $A L$ . See the read/write tension in Static Noise Margin (SNM).

Exercise 4.3

Compare the storage principle of the 6T SRAM cell with the DRAM 1T1C cell. Why does one need refresh and the other doesn't, even though both are volatile?

Recall Solution

DRAM 1T1C stores charge on a passive capacitor. Charge leaks away through junction and subthreshold paths, so the bit decays in milliseconds → it must be refreshed periodically.
6T SRAM stores the bit in an active feedback loop of two inverters. The loop is powered by $V_{D D}$ and continuously regenerates the node voltages, refilling any leaked charge automatically → no refresh.
Both lose data at power-off (both volatile), but only the passive-storage DRAM needs refresh. Volatile is about power; static/dynamic is about whether an active loop restores the bit.

Level 5 — Mastery

Exercise 5.1

A process gives you these fixed strengths (in arbitrary current units, proportional to $W / L$ ): $N L = 2.4$ , $P L = 0.9$ , and access $A L = 1.2$ . (a) Compute $C R$ and $PUR$ . (b) The rules are $C R \geq 1.2$ and $PUR \leq 1.8$ . Does the cell pass? (c) If the foundry now shrinks the access transistor to $A L = 0.8$ , recompute both ratios and re-check. What happened to read vs write margin?

Recall Solution

(a) $C R = \frac{2.4}{1.2} = 2.0$ , $PUR = \frac{0.9}{1.2} = 0.75$ . (b) $C R = 2.0 \geq 1.2 ✓$ and $PUR = 0.75 \leq 1.8 ✓$ → passes both. (c) With $A L = 0.8$ : $C R = \frac{2.4}{0.8} = 3.0, PUR = \frac{0.9}{0.8} = 1.125.$

$C R$ rose $2.0 \to 3.0$ : read margin improved — the pull-down $N L$ now dominates the smaller access door even more, so $V_{r e a d}$ sits even further below the trip point.
$PUR$ rose $0.75 \to 1.125$ : still $\leq 1.8$ , so the write rule still passes, but the number moved closer to the limit — a weaker access door has less muscle to overpower the PMOS pull-up, so the cell became harder to write.
Net: shrinking access improves read margin and erodes write margin — the exact read/write trade-off that governs SRAM sizing.

Exercise 5.2

Full read-cycle trace. Cell holds $Q = 1, QB = 0$ , $V_{D D} = 1.0 V$ . Both bit lines precharged to $1.0 V$ . Walk the cycle step by step (assert, discharge path, $Δ V$ sign, sense) and state the read value. Then explain in one sentence why $C R$ mattered even though we stored a $1$ on $Q$ .

Recall Solution

Precharge: $B L = B L B = 1.0 V$ . Why: start both lines equal so a small difference is meaningful.
Assert $W L = 1$ : doors $A L, A R$ open. Why: connect nodes to lines for sensing.
Discharge path: $QB = 0$ sinks through $A R + N R$ , so $B L B$ falls; $Q = 1$ has no sink, so $B L$ stays $\approx 1.0 V$ .
Differential: $Δ V = V_{B L} - V_{B L B} > 0$ (positive).
Sense: the Sense Amplifier sees $Δ V > 0$ and reports a stored 1. ✓ Why $C R$ still mattered: on the other side, precharged $B L B$ injects current into $QB = 0$ through $A R$ ; $C R$ (via $N R$ / $A R$ ) keeps $QB$ from rising past the trip point, so the stored bit survives the read.

Exercise 5.3

Prove the design intuition symbolically. Assume the read-disturb voltage on the " $0$ " node follows the first-order model $V_{r e a d} = \frac{V _{D D}}{1 + C R}$ . If $V_{D D} = 1.0 V$ and the inverter trip point is $V_{t r i p} = 0.4 V$ , find the minimum $C R$ that keeps $V_{r e a d} < V_{t r i p}$ .

Recall Solution

We require the disturb voltage to stay below the trip point $V_{t r i p}$ (the input at which inverter B would start switching):

\;\Rightarrow\;CR>1.5.$$ So the **minimum cell ratio is $CR=1.5$**. Any $CR\ge1.5$ keeps the read-disturb voltage below the trip point → the cell is read-stable. This is exactly why real designs use $CR$ in the $1.5$–$2$ range: it buys margin above this hard floor.

Active recall

Recall One-line self-tests

Which ratio guards READ? ::: $C R = (W / L)_{N L} / (W / L)_{A L}$ Which ratio guards WRITE? ::: $PUR = (W / L)_{P L} / (W / L)_{A L}$ Read wants pull-down… ::: strong (large $C R$ ) Write wants pull-up… ::: weak (small $PUR$ ) Is the metastable middle point stable? ::: No — loop gain $> 1$ there How do writes actually flip a node? ::: by pulling the opposite node LOW, not pushing a node high Why no refresh in SRAM? ::: the active feedback loop regenerates the bit continuously What is the trip point? ::: the input voltage at which an inverter switches high↔low What does "loop gain" equal on the g-curve? ::: the slope of g at that point