CMOS inverter structure and operation: Foundations

Before you can read a single line of the parent note, you need to know what each squiggle means and what picture lives behind it. This page builds them all, from the very bottom, in the order they lean on each other.

1. Voltage — the "height of electric water"

Why the topic needs it: the whole inverter is a story about output voltage rising to a "full tank" ( $V_{D D}$ ) or draining to an "empty tank" (ground). Every symbol below is some voltage or a difference of voltages.

2. Voltage difference — why we always write two subscripts

A single voltage is a height. But a switch cares about a difference in height — how much higher one terminal is than another. That is why the parent note is full of symbols like $V_{GS}$ with two letters.

Why the topic needs it: a transistor doesn't ask "is my gate high?" It asks "is my gate high compared to my source?" — a difference. Get this wrong and the PMOS analysis collapses.

3. The MOSFET — a switch you turn with voltage

Look at the figure: the gate is a plate held near a channel but not touching it. Push enough voltage on that plate and it "pulls" a conducting bridge into existence between source and drain. Remove it and the bridge vanishes.

4. Threshold voltage $V_{t}$ — the tripping point

Why the topic needs it: $V_{t}$ is the number that decides which switch is open at every input. The five VTC regions and the switching threshold $V_{M}$ are all defined by comparing $V_{in}$ against these thresholds.

5. Source vs Drain — and why placement matters

This is the whole reason the parent can write $V_{GS, n} = V_{in}$ but $V_{GS, p} = V_{in} - V_{D D}$ : the two transistors have their sources tied to different references. See MOSFET operating regions for the linear/saturation detail behind "ON."

6. The inverter as two switches — the master picture

7. Capacitance $C_{L}$ — why output can't flip instantly

Why the topic needs it: to switch the output HIGH you must fill this bucket with charge; to switch LOW you must empty it. That takes time (the S-curve isn't a vertical cliff → see Propagation delay and transistor sizing) and it costs energy every cycle (the source of dynamic power → see Dynamic power and clock frequency).

V_{X Y}

mean, in words?

The voltage at X minus the voltage at Y — a drop from X down to Y.

What are

V_{D D}

and GND physically?

The full ("HIGH", logic 1) and empty ("LOW", logic 0) reference levels of the circuit.

Which three terminals does a MOSFET have, and which controls it?

Gate, Source, Drain; the Gate voltage controls whether Source–Drain conducts.

When is an NMOS ON?

When

V_{GS} > V_{t n}

(gate pushed high enough above its source).

When is a PMOS ON, and what is the sign of

V_{tp}

When

V_{GS} < V_{tp}

with

V_{tp} < 0

— gate pulled at least

∣ V_{tp} ∣

below its source.

Why is PMOS drawn on top (pull-up) and NMOS on bottom (pull-down)?

PMOS passes a clean HIGH and NMOS a clean LOW, so each is placed where it delivers the value it passes well.

What is

C_{L}

and why does it matter?

The load capacitor — a charge "bucket" the output must fill/empty, causing delay and dynamic power.

What do

f

and

α

stand for in the power formula?

f

= switching frequency (ticks/s);

α

= fraction of ticks where the output actually flips.

Why does switching energy scale with

V_{D D}^{2}

Charge moved

\propto V_{D D}

and each charge falls through

\sim V_{D D}

, so energy = charge × voltage

\propto V_{D D}^{2}

What does the overline in

\overline{V_{in}}

mean?

Logical NOT — the opposite value.

Foundations — CMOS inverter structure and operation

1. Voltage — the "height of electric water"

2. Voltage difference — why we always write two subscripts

3. The MOSFET — a switch you turn with voltage

4. Threshold voltage $V_{t}$ — the tripping point

5. Source vs Drain — and why placement matters

6. The inverter as two switches — the master picture

7. Capacitance $C_{L}$ — why output can't flip instantly

8. Frequency $f$ , probability $α$ , and charge — the power symbols

9. The overline and inequalities — small notation, big meaning

Prerequisite map

Equipment checklist