CMOS inverter structure and operation: Question bank

This page is a trap course. Each item below is designed to catch a specific misconception or an overlooked boundary case from CMOS inverter structure and operation. Read the prompt, commit to an answer out loud, then reveal. The answer side always gives the reasoning, never a bare verdict.

Before you start, three words we will lean on:

Pull-up = the transistor (PMOS) that connects the output up to $V_{D D}$ .
Pull-down = the transistor (NMOS) that connects the output down to GND.
Steady state = the input has settled to a clean 0 or a clean $V_{D D}$ and stopped moving.

True or false — justify

A CMOS inverter dissipates no power at all.

False — it dissipates almost no static power (one transistor is always OFF in steady state), but it burns dynamic power

α C_{L} V_{D D}^{2} f

every time the output switches, plus tiny leakage. See Dynamic power and clock frequency.

In steady logic-1 or logic-0, both transistors are OFF.

False — exactly one is ON and one OFF. The ON device holds the output firmly at

V_{D D}

or GND; if both were OFF the output would float. Both-ON happens only during the switching instant.

The output of the inverter is connected to

V_{D D}

and GND at the same time in steady state.

False — that would be a short circuit. In steady state one of the two series switches is open, so there is no continuous path from

V_{D D}

to GND. That broken path is the whole reason static current ≈ 0.

Lowering

V_{D D}

by half cuts dynamic power roughly in half.

False — dynamic power scales with

V_{D D}^{2}

, so halving

V_{D D}

cuts it to about one quarter. The quadratic is exactly why supply-voltage scaling is the strongest power lever.

PMOS is made wider than NMOS because PMOS is the stronger device.

False — it's the opposite: holes are ~2–3× slower than electrons, so a same-size PMOS is weaker. We widen it to compensate and equalize the strengths. See Propagation delay and transistor sizing.

The switching threshold

V_{M}

is always exactly

V_{D D} /2

False —

V_{M} = V_{D D} /2

only for a symmetric inverter (

k_{n} = k_{p}

). If the PMOS is too narrow,

V_{M}

shifts lower; if too wide, it shifts higher.

Because the VTC transition is not vertical, digital logic is unreliable.

False — the flat rails on either side of the transition are what give robustness: a whole range of noisy inputs maps to a clean output. The steepness in the middle is a bonus, not a requirement.

At the switching threshold

V_{M}

, both transistors are cut off.

False — at

V_{M}

both are in saturation and conducting equal current. This brief both-ON state is precisely the source of short-circuit current during a transition.

The logic function

V_{o u t} = \overline{V_{in}}

was an assumption we fed into the circuit.

False — it is derived from the complementary ON/OFF conditions (

V_{GS, n} = V_{in}

V_{GS, p} = V_{in} - V_{D D}

). The inversion falls out of the physics; it is not postulated.

Noise margins depend on how fast the clock runs.

False — noise margins (

N M_{H} = V_{O H} - V_{I H}

N M_{L} = V_{I L} - V_{O L}

) are static properties read off the VTC. Clock speed affects dynamic power and delay, not the DC margins. See Noise margins in digital logic.

Spot the error

"NMOS turns ON when its gate is LOW."

Wrong — NMOS turns ON when its gate is HIGH (

V_{GS, n} = V_{in} > V_{t n}

). It is the PMOS that turns ON when its gate is LOW. Swapping these is the single most common CMOS error.

"For the PMOS, it conducts when

V_{GS} > V_{t}

, just like the NMOS."

Wrong on the sign. PMOS has

V_{tp} < 0

and turns ON when

V_{GS, p} < V_{tp}

— i.e. the gate must be below the source by more than

∣ V_{tp} ∣

. The inequality flips because the carrier type flips.

"Put NMOS on top as the pull-up since it carries more current."

Wrong placement. NMOS passes a strong 0 but a degraded 1 (output would only reach

V_{D D} - V_{t n}

). The pull-up must deliver a clean HIGH, so it must be the PMOS. Placement follows which value the device passes cleanly, not raw current.

"Static power is zero, so a chip with a billion idle gates draws zero current."

Wrong for real chips — classical static power is negligible, but leakage (subthreshold + gate) through the "OFF" transistor is nonzero and adds up over a billion gates. See Leakage and short-channel effects.

"During the

0 \to 1

output transition, all the capacitor energy comes out of

V_{D D}

and none is wasted."

Wrong — of the energy drawn from

V_{D D}

, half is stored on

C_{L}

(

\frac{1}{2} C_{L} V_{D D}^{2}

) and the other half is dissipated as heat in the PMOS. On the way down, the stored half is dumped as heat in the NMOS.

V_{M}

is where the VTC slope equals

- 1

Wrong — the slope-

= - 1

points define

V_{I L}

and

V_{I H}

(the noise-margin corners).

V_{M}

is where the VTC crosses the 45° line

V_{o u t} = V_{in}

Why questions

Why does the inverter guarantee that output is always the opposite of input, for any valid logic level?

Both transistors share the same gate input but respond to it in opposite ways, so for a clean 0 or 1 exactly one is ON — it hands the output to

V_{D D}

or GND, never both, never neither.

Why is

V_{D D}^{2}

(not

V_{D D}

) in the dynamic power formula?

Energy per switching event is charge moved (

\propto C_{L} V_{D D}

) times the voltage it moves through (

V_{D D}

), giving

C_{L} V_{D D}^{2}

. Two voltage factors → the square.

Why do we want

k_{n} = k_{p}

for a "good" inverter?

Equal

k

makes pull-up and pull-down equally strong, which centers

V_{M}

V_{D D} /2

(symmetric, largest noise margins) and equalizes rise and fall times.

Why is CMOS said to have the "largest possible" noise margins?

Because

V_{O H} = V_{D D}

and

V_{O L} = 0

exactly — the output swings the full rail with no threshold drop, so both margins are as wide as the supply allows.

Why does short-circuit current exist at all if one device is "always OFF"?

"Always one OFF" is only true in steady state. During the input's brief passage through the mid-region,

V_{in}

is simultaneously above

V_{t n}

and below

V_{D D} + ∣ V_{tp} ∣

, so both conduct for that instant.

Why does the same inverter design carry over to NAND and NOR gates?

The inverter fixes the core recipe — complementary pull-up and pull-down networks driven by the same inputs. NAND/NOR just replace the single transistors with series/parallel networks of the same idea. See CMOS logic gates (NAND NOR).

Why can't we just make both transistors tiny to save area and power?

Smaller

W / L

weakens drive current, which slows charging/discharging of

C_{L}

→ larger propagation delay. Sizing trades area and speed; it can't be shrunk freely.

Edge cases

What happens to the output if the input sits exactly at

V_{M}

and stays there?

Both transistors conduct in saturation and a steady short-circuit current flows from

V_{D D}

to GND — a wasteful, undefined-logic state. Real inputs sweep through

V_{M}

quickly precisely to avoid lingering here.

What is the output when the input is a "weak" HIGH of only

V_{t n}

(just barely above threshold)?

The NMOS is only weakly ON and the PMOS may still be partly ON, so the output sits somewhere mid-rail — an invalid logic level. This is why clean inputs must exceed

V_{I H}

, not just

V_{t n}

. See MOSFET operating regions.

If the PMOS gate were accidentally tied to

V_{D D}

permanently (not to the input), what does the inverter do?

The PMOS is forced OFF forever, so the output can only be pulled low or left floating — it loses its ability to produce a HIGH and no longer inverts.

At input

V_{in} = 0

exactly, in which region is each transistor?

NMOS is fully OFF (

V_{GS, n} = 0 < V_{t n}

); PMOS is ON in the linear/triode region (

V_{GS, p} = - V_{D D}

, deep on), so it pulls the output cleanly to

V_{D D}

with no current flowing.

V_{D D}

is scaled down toward the threshold voltages, what breaks?

When

V_{D D}

approaches

V_{t n} + ∣ V_{tp} ∣

, there is little or no input range where both devices are properly ON/OFF with margin; noise margins shrink and the gate stops switching reliably. This sets a floor on supply scaling.

What happens to

V_{M}

if hole mobility drops (older/hotter process) but sizes stay fixed?

The PMOS gets relatively weaker, so

k_{p} < k_{n}

; the pull-down wins the tug-of-war and

V_{M}

shifts below

V_{D D} /2

, degrading the low-side margin and making rise slower than fall.

Recall One-line summary of the traps

Static ≈ 0 but dynamic ≠ 0; both-ON only during switching; PMOS wider because it's weaker; $V_{M} = V_{D D} /2$ only when symmetric; margins are static, power is dynamic; and PMOS-up / NMOS-down is dictated by which value each passes cleanly.