CMOS inverter structure and operation: Visual walkthrough

Step 1 — What a single MOSFET actually does: a valve

WHAT. Forget transistors for a moment. Picture a garden tap (a valve) on a pipe. Water flows only when you open the tap. A MOSFET is an electrical valve: a small control terminal decides whether current is allowed to flow through the main channel.

The three terminals we care about:

Gate (G) — the tap handle. It carries almost no current; it only controls.
Source (S) — where the carriers come from.
Drain (D) — where they flow to.

WHY introduce a valve first. The whole inverter is two of these valves stacked. If you understand one valve's ON/OFF rule, the rest is bookkeeping. We need one number to describe "how hard is the tap being turned": the gate-to-source voltage, written $V_{GS}$ , which just means "gate voltage minus source voltage."

$V_{GS} = voltage at the handle V_{G} - voltage at the inflow V_{S}$

PICTURE. The red handle is the gate. When we push it past a critical amount, the channel opens.

Figure — CMOS inverter structure and operation

Step 2 — Two valves, opposite handles: the complementary pair

WHAT. Take two valves and wire them so the same wire drives both handles. Call that shared wire the input, $V_{in}$ . Stack them between the power rail $V_{D D}$ (the "full tank") and ground GND (the drain, 0 V).

Top valve = PMOS: its source sits at $V_{D D}$ .
Bottom valve = NMOS: its source sits at GND.
The point where they meet is the output, $V_{o u t}$ .

WHY wire them to the same input. This is the trick that makes inversion automatic. Because NMOS opens on a high handle and PMOS opens on a low handle, one input can never open both the same way. Let us prove it with the actual gate-to-source voltages.

For the NMOS (source at $0$ ): $V_{GS, n} = V_{in} - 0 = input V_{in} \Rightarrow ON when V_{in} > V_{t n}$

For the PMOS (source at $V_{D D}$ ): $V_{GS, p} = input V_{in} - its source V_{D D} \Rightarrow ON when V_{in} - V_{D D} < V_{tp}$

The PMOS condition rearranges to $V_{in} < V_{D D} + V_{tp}$ . Since $V_{tp} < 0$ , that means " $V_{in}$ low enough." So a high input opens the bottom, a low input opens the top — never the same one.

PICTURE. The red input wire feeds both handles at once.

Step 3 — Input LOW: the top valve wins

WHAT. Set $V_{in} = 0$ . Check each valve.

NMOS: $V_{GS, n} = 0$ , which is not $> V_{t n}$ → OFF (bottom shut).
PMOS: $V_{GS, p} = 0 - V_{D D} = - V_{D D}$ , which is $< V_{tp}$ → ON (top open).

WHY this gives HIGH out. With the top open and the bottom shut, the output is connected straight to the full tank $V_{D D}$ and disconnected from ground. Charge flows in until the output sits at $V_{D D}$ , then stops. No path exists from $V_{D D}$ to GND, so no steady current flows — this is the near-zero static power the parent note promised.

$V_{in} = 0 \Rightarrow PMOS ON, NMOS OFF \Rightarrow V_{o u t} = V_{D D}$

PICTURE. Red = the live path from $V_{D D}$ to the output. The bottom is a broken (shut) valve.

Step 4 — Input HIGH: the bottom valve wins

WHAT. Set $V_{in} = V_{D D}$ . Check each valve.

NMOS: $V_{GS, n} = V_{D D} > V_{t n}$ → ON (bottom open).
PMOS: $V_{GS, p} = V_{D D} - V_{D D} = 0$ , which is not $< V_{tp}$ → OFF (top shut).

WHY this gives LOW out. Now the output is connected to ground and cut off from the tank. Any charge sitting on the output drains away until $V_{o u t} = 0$ . Again exactly one valve is shut, so no $V_{D D}$ -to-GND current flows in steady state.

$V_{in} = V_{D D} \Rightarrow NMOS ON, PMOS OFF \Rightarrow V_{o u t} = 0$

Steps 3 and 4 together are the inversion, derived not assumed: $V_{o u t} = \overline{V_{in}}$

PICTURE. Red = the live pull-down path to ground; the top is shut.

Step 5 — The messy middle: sweeping $V_{in}$ from 0 to $V_{D D}$

WHAT. Real inputs don't teleport from 0 to $V_{D D}$ ; they slide. As $V_{in}$ rises, we pass through five regimes. Plot $V_{o u t}$ against $V_{in}$ — this is the Voltage Transfer Characteristic (VTC).

$V_{in} < V_{t n}$ : NMOS OFF, PMOS fully ON → flat top, $V_{o u t} = V_{D D}$ .
NMOS just cracks open, PMOS still strong → output eases down a little.
Both valves half-open and fighting → the curve plunges steeply.
PMOS weakening, NMOS strong → output eases toward 0.
$V_{in} > V_{D D} + V_{tp}$ : PMOS OFF, NMOS fully ON → flat bottom, $V_{o u t} = 0$ .

WHY it is an S (backwards) shape. In regions 1 and 5 one valve is fully shut, so the output is pinned to a rail — nothing to change, hence flat. In the middle both are partly open and small input changes tip the balance hard, hence steep. The steep middle is what makes a digital device out of analog transistors: it hates the in-between and snaps to a rail.

PICTURE. The red curve is the VTC; the five regions are labelled along it.

Step 6 — The switching threshold $V_{M}$ : where the two valves tie

WHAT. Somewhere in the plunge, $V_{o u t}$ equals $V_{in}$ — the VTC crosses the 45° line. Call that input the switching threshold $V_{M}$ . Here both transistors are saturated (fully "trying") and carry equal current, because at this crossing neither is winning.

WHY set the currents equal. If more current flowed down (NMOS) than in (PMOS), the output would keep falling — so it isn't the balance point. Balance means the pull-up current equals the pull-down current. Writing both saturation currents and setting them equal gives:

$V_{M} = \frac{V _{D D} + V _{tp} + V _{t n} k _{n} / k _{p}}{1 + k _{n} / k _{p}}$

Term by term:

$V_{D D}, V_{t n}, V_{tp}$ — the supply and the two thresholds (with $V_{tp} < 0$ ).
$k_{n} = μ_{n} C_{o x} (W / L)_{n}$ — the NMOS "strength": mobility $μ_{n}$ (how fast its electrons move) times oxide capacitance $C_{o x}$ times width-over-length shape $W / L$ .
$k_{p}$ — the same for the PMOS (uses hole mobility $μ_{p}$ ).
$k_{n} / k_{p}$ — the strength ratio that tilts $V_{M}$ toward whichever valve is stronger.

For a symmetric inverter we want $V_{M} = V_{D D} /2$ (equal noise margins, equal rise/fall). Plug $V_{M} = V_{D D} /2$ in and it demands $k_{n} = k_{p}$ .

WHY PMOS must be wider. Holes are 2–3× slower than electrons, so $μ_{p} \approx μ_{n} /2.5$ . To make $k_{n} = k_{p}$ with the same $L$ , widen the PMOS: $(W / L)_{p} = \frac{μ _{n}}{μ _{p}} (W / L)_{n} \approx 2.5 (W / L)_{n}$

PICTURE. Red dot = the crossing of the VTC with the 45° line at $V_{M} = V_{D D} /2$ .

Step 7 — The degenerate cases: rails, and the brief both-on spike

WHAT. Two edges the reader must never be surprised by.

Rail inputs (already covered, now on the picture). At $V_{in} = 0$ and $V_{in} = V_{D D}$ the output sits exactly on a rail: $V_{O H} = V_{D D}$ , $V_{O L} = 0$ . This full-rail swing is why CMOS has the largest possible noise margins — see Noise margins in digital logic.

The transition spike. Right at $V_{M}$ both valves are momentarily open, so a small current does briefly flow from $V_{D D}$ to GND — the short-circuit current. It exists only during the nanosecond of switching, not in steady state. Together with charging the load, it makes the switching (dynamic) power:

$P_{d y n} = switch prob. α load cap C_{L} energy \propto charge \times voltage V_{D D}^{2} clock rate f$

The $V_{D D}^{2}$ is why lowering the supply is the strongest power lever — see Dynamic power and clock frequency. And "static power $\approx 0$ " holds only ideally; real chips leak, per Leakage and short-channel effects.

WHY show this as a step. The naive story "one valve always shut" is steady-state true but skips the transition. A complete picture must show the spike so the reader knows where power actually goes.

PICTURE. Red = the current spike, plotted against $V_{in}$ , peaking exactly at $V_{M}$ .

The one-picture summary

Everything above collapses into one figure: the input wire feeds both valves; the VTC shows the flat rails and the steep middle; the balance point $V_{M}$ sits on the 45° line; and the current spike lives exactly there.

Recall Feynman: the whole walkthrough in plain words

A transistor is a valve with a handle. Stack two valves between a full tank (power) and a drain (ground), and wire both handles to the same wire (the input). One valve is built to open when you push the handle up; the other opens when you push it down. So whichever way you push, one opens and one shuts — and the meeting point in the middle gets pulled to the opposite rail from where you pushed. Push up (input HIGH) → bottom opens → output drains to ground (LOW). Push down (input LOW) → top opens → output fills to the tank (HIGH). Because one valve is always shut, no water runs straight through in steady state — that's the near-zero power. If you slide the handle slowly, there's a moment in the exact middle where both valves crack open at once and current briefly rushes through; that middle point is $V_{M}$ , ideally halfway. To make that middle sit dead-center, we widen the slower valve (the PMOS, ~2.5×) so both are equally strong. That's the entire inverter — and every other CMOS gate is just more valves wired by the same up/down logic (see CMOS logic gates (NAND NOR)).

Recall

The condition for the NMOS to conduct ::: $V_{GS, n} = V_{in} > V_{t n}$ The condition for the PMOS to conduct ::: $V_{in} - V_{D D} < V_{tp}$ (input low enough, $V_{tp} < 0$ ) What happens at $V_{M}$ ::: both transistors saturated, equal current, VTC crosses the 45° line Why widen the PMOS ~2.5× ::: hole mobility is ~2.5× lower, so wider $W$ restores $k_{p} = k_{n}$