CMOS inverter structure and operation: Worked examples

This page is a drill. The parent note built the theory; here we hit every case class with numbers. Guess before you read the steps — that "Forecast" habit is how you learn to feel the circuit.

Before we start, one reminder of the symbols we will reuse (all built in the parent):

Definition Symbol refresher (plain words)

$V_{D D}$ — the supply voltage, the "battery" the top of the circuit is tied to.
$V_{in}$ — the voltage we feed in at the shared gates.
$V_{o u t}$ — the voltage at the shared drains (the answer the gate produces).
$V_{t n}$ — NMOS threshold: input must climb above this for NMOS to switch ON. Positive.
$V_{tp}$ — PMOS threshold. Negative. PMOS switches ON when its gate is below its source by more than $∣ V_{tp} ∣$ .
$k_{n} = μ_{n} C_{o x} (W / L)_{n}$ — the NMOS "strength knob" (how much current it pushes per volt $^{2}$ ). $k_{p}$ is the PMOS one.
$C_{L}$ — the load capacitor: everything hanging off the output that must be charged/discharged. Measured in farads (F); $1 fF = 1 0^{- 15} F$ .
$f$ — switching frequency (events per second, in Hz). $α$ — activity factor (fraction of clocks that actually toggle, between 0 and 1).

The scenario matrix

Every question this topic can ask falls into one of these cells. Each worked example below is tagged with the cell(s) it covers.

#	Cell (case class)	What's tricky about it	Example
C1	Input LOW (clean 0)	Which device is ON? Output?	Ex 1
C2	Input HIGH (clean 1)	Mirror of C1, sign of $V_{GS, p}$	Ex 2
C3	Sign of $V_{tp}$ (degenerate: is PMOS ON at a given $V_{in}$ ?)	Negative threshold trips people	Ex 3
C4	Switching point $V_{M}$ (both saturated)	Formula with $k_{n} / k_{p}$	Ex 4
C5	Sizing (limiting: force $V_{M} = V_{D D} /2$ )	Solve for $(W / L)_{p}$	Ex 5
C6	Dynamic power (real-world word problem)	Units fF, GHz, $α$	Ex 6
C7	Voltage scaling (limiting behaviour of $V_{D D}^{2}$ )	Quadratic, not linear	Ex 7
C8	Noise margins (both flat regions)	$N M_{H}$ and $N M_{L}$	Ex 8
C9	Degraded pass (NMOS as pull-up — the "wrong" circuit)	Output loses $V_{t n}$	Ex 9
C10	Exam twist ( $V_{in}$ in the transition band)	Both ON → short-circuit current	Ex 10

Figure — CMOS inverter structure and operation

Throughout, unless a problem says otherwise, take $V_{D D} = 1.0 V$ , $V_{t n} = + 0.3 V$ , $V_{tp} = - 0.3 V$ .

Ex 1 — Clean LOW input (cell C1)

Worked example

Statement: $V_{in} = 0 V$ . Which transistor conducts, and what is $V_{o u t}$ ?

Forecast: Input is LOW, so guess the output is... HIGH? Which device pulls it there?

Step 1 — Test the NMOS. Its source sits at GND, so $V_{GS, n} = V_{in} - 0 = 0 V$ . Compare to $V_{t n} = 0.3$ : since $0 < 0.3$ , NMOS is OFF. Why this step? A MOSFET only conducts once $V_{GS}$ crosses its threshold; we must check that first, always.

Step 2 — Test the PMOS. Its source sits at $V_{D D} = 1$ , so $V_{GS, p} = V_{in} - V_{D D} = 0 - 1 = - 1 V$ . PMOS turns ON when $V_{GS, p} < V_{tp} = - 0.3$ . Since $- 1 < - 0.3$ , PMOS is ON. Why this step? PMOS uses the opposite comparison (a strictly negative threshold); checking it confirms the complementary pair really is complementary.

Step 3 — Read the output. Only the PMOS conducts, connecting output straight to $V_{D D}$ . So $V_{o u t} = V_{D D} = 1 V$ (HIGH). Why this step? With one path open and one closed, the open path is the answer — no current flows, no voltage drop, output = whatever the ON device connects to.

Verify: Output HIGH when input LOW = inversion. ✓ And $V_{o u t} = V_{D D}$ exactly (PMOS passes a strong 1, no lost threshold). Units: volts throughout. ✓

Ex 2 — Clean HIGH input (cell C2)

Ex 3 — The sign of $V_{tp}$ , a degenerate check (cell C3)

Worked example

Statement: Same inverter, but now feed $V_{in} = 0.6 V$ . Is the PMOS ON or OFF? (This is the trap where people forget $V_{tp} < 0$ .)

Forecast: Guess ON or OFF before computing.

Step 1 — Write $V_{GS, p}$ . $V_{GS, p} = V_{in} - V_{D D} = 0.6 - 1.0 = - 0.4 V$ . Why? PMOS conduction is governed by gate-relative-to-source, and its source is $V_{D D}$ , not ground.

Step 2 — Apply the PMOS rule with the correct sign. ON iff $V_{GS, p} < V_{tp}$ , i.e. $- 0.4 < - 0.3$ . That is true → PMOS is ON. Why? $- 0.4$ is more negative than $- 0.3$ , so the overdrive $∣ V_{GS, p} ∣ - ∣ V_{tp} ∣ = 0.4 - 0.3 = 0.1 V$ is positive. The classic mistake is comparing magnitudes as if $V_{tp}$ were $+ 0.3$ , which flips the answer.

Step 3 — Cross-check NMOS. $V_{GS, n} = 0.6 > 0.3$ → NMOS also ON. So at $V_{in} = 0.6$ both conduct — we're inside the transition band (revisited in Ex 10). Why? Confirms consistency: near mid-supply neither device is fully off, which is exactly why the VTC has a sloped middle.

Verify: PMOS overdrive $= + 0.1 V > 0$ → conducting. ✓ If you had (wrongly) used $V_{tp} = + 0.3$ you'd get $- 0.4 < + 0.3$ "ON" by luck here, but at $V_{in} = 0.8$ the wrong rule breaks — do that as a self-test.

Ex 4 — Switching threshold $V_{M}$ (cell C4)

Worked example

Statement: Compute $V_{M}$ for $V_{D D} = 1.0$ , $V_{t n} = 0.3$ , $V_{tp} = - 0.3$ , and $k_{n} / k_{p} = 2.25$ (an unbalanced, NMOS-strong inverter).

Forecast: With NMOS stronger, does $V_{M}$ sit above or below $V_{D D} /2 = 0.5$ ?

Step 1 — Recall the formula (derived in the parent by setting the two saturation currents equal): $V_{M} = \frac{V _{D D} + V _{tp} + V _{t n} k _{n} / k _{p}}{1 + k _{n} / k _{p}} .$ Why this tool? At $V_{M}$ both transistors are saturated and carry equal current; equating their saturation currents is the only condition that pins the crossover, and it yields exactly this weighted average.

Step 2 — Evaluate the root. $k_{n} / k_{p} = 2.25 = 1.5$ . Why? The ratio enters only through its square root because saturation current scales with $k$ , and the current-balance equation is quadratic in $(V_{GS} - V_{t})$ .

Step 3 — Plug in. Numerator $= 1.0 + (- 0.3) + 0.3 (1.5) = 1.0 - 0.3 + 0.45 = 1.15$ . Denominator $= 1 + 1.5 = 2.5$ . So $V_{M} = 1.15/2.5 = 0.46 V$ . Why? Substitution.

Verify: $V_{M} = 0.46 < 0.5$ . A stronger NMOS pulls the crossover down (it wins the tug-of-war earlier). ✓ Sanity: if instead $k_{n} = k_{p}$ (root $= 1$ ), $V_{M} = (1 - 0.3 + 0.3) /2 = 0.5 = V_{D D} /2$ exactly — symmetric, as expected. ✓

Ex 5 — Sizing for a symmetric inverter (limiting case C5)

Worked example

Statement: Electron mobility $μ_{n} = 2.5 μ_{p}$ , equal channel lengths, and $(W / L)_{n} = 2$ . Find $(W / L)_{p}$ that forces $V_{M} = V_{D D} /2$ .

Forecast: Bigger or smaller than the NMOS? By what factor?

Step 1 — Symmetry condition. $V_{M} = V_{D D} /2$ requires $k_{n} = k_{p}$ (from Ex 4's sanity check). Why? Only equal strengths make the crossover land dead-centre and give equal rise/fall.

Step 2 — Expand $k_{n} = k_{p}$ . $μ_{n} C_{o x} (W / L)_{n} = μ_{p} C_{o x} (W / L)_{p}$ . Cancel $C_{o x}$ : $μ_{n} (W / L)_{n} = μ_{p} (W / L)_{p} .$ Why? $C_{o x}$ (oxide capacitance per area) is identical for both devices on the same process, so it drops out — mobility is the only asymmetry left.

Step 3 — Solve. $(W / L)_{p} = \frac{μ _{n}}{μ _{p}} (W / L)_{n} = 2.5 \times 2 = 5$ . Why? Holes are 2.5× slower than electrons, so PMOS must be 2.5× wider to push equal current.

Verify: Ratio $(W / L)_{p} / (W / L)_{n} = 5/2 = 2.5 = μ_{n} / μ_{p}$ . ✓ Falls in the textbook "2–3×" range. ✓ Units: $W / L$ is dimensionless. ✓

Ex 6 — Dynamic power, real-world word problem (cell C6)

Worked example

Statement: A datapath has $10, 000$ identical inverters. Each: $C_{L} = 50 fF$ , $V_{D D} = 1.0 V$ , clocked at $f = 1 GHz$ , activity $α = 0.2$ . Find total dynamic power.

Forecast: Micro-, milli-, or watts?

Step 1 — Per-gate formula. $P_{d y n} = α C_{L} V_{D D}^{2} f$ . Why this tool? Each toggle moves charge $C_{L} V_{D D}$ across the supply, dissipating $C_{L} V_{D D}^{2}$ per full cycle; multiply by how often ( $α f$ ) to get power.

Step 2 — Substitute (SI units!). $C_{L} = 50 \times 1 0^{- 15} F$ , $f = 1 0^{9} Hz$ : $P_{1} = 0.2 \times 50 \times 1 0^{- 15} \times 1. 0^{2} \times 1 0^{9} = 1.0 \times 1 0^{- 5} W = 10 μ W .$ Why? Convert fF→F and GHz→Hz before multiplying, or the exponents scramble.

Step 3 — Scale to the array. $P_{t o t} = 10, 000 \times 10 μ W = 1 0^{5} μ W = 0.1 W = 100 mW$ . Why? Independent gates just add their powers.

Verify: Dimensional check: $[F] [V^{2}] [Hz] = \frac{C}{V} \cdot V^{2} \cdot \frac{1}{s} = \frac{C \cdot V}{s} = \frac{J}{s} = W$ . ✓ Per-gate $10 μ W$ matches the parent's worked value. ✓

Ex 7 — Voltage scaling, the quadratic lever (limiting case C7)

Worked example

Statement: Same gate as Ex 6, but drop $V_{D D}$ from $1.0 V$ to $0.7 V$ (holding $C_{L}, f, α$ ). By what factor does dynamic power fall? Also state the linear-intuition answer people wrongly expect.

Forecast: Voltage went to 70%. Power to... 70%? Less?

Step 1 — Only $V_{D D}^{2}$ changes. $\frac{P _{n e w}}{P _{o l d}} = (\frac{V _{D D, n e w}}{V _{D D, o l d}})^{2} = (0.7)^{2} = 0.49$ . Why this tool? In $P = α C_{L} V_{D D}^{2} f$ every other factor is fixed, so the ratio is purely the square of the voltage ratio. Squaring is the whole point — energy per event scales with charge and the voltage that charge falls through.

Step 2 — Numbers. $P_{n e w} = 0.49 \times 10 μ W = 4.9 μ W$ per gate. Why? Multiply the old per-gate power by $0.49$ .

Step 3 — Contrast the wrong linear guess. A linear expectation gives $0.70 \times 10 = 7.0 μ W$ — that overestimates by $\approx 43%$ . The extra saving is exactly why voltage scaling is the strongest power knob. Why? It cements the " $V_{D D}^{2}$ , not $V_{D D}$ " lesson.

Verify: $0. 7^{2} = 0.49$ ; $0.49 \times 10 = 4.9$ . ✓ Saving $= 1 - 0.49 = 51%$ from a mere $30%$ voltage cut. ✓

Ex 8 — Noise margins (both flat regions, cell C8)

Worked example

Statement: A CMOS inverter measures $V_{O H} = 1.0$ , $V_{O L} = 0$ , and from its VTC the unity-slope points are $V_{I L} = 0.42 V$ , $V_{I H} = 0.58 V$ . Compute $N M_{H}$ and $N M_{L}$ .

Forecast: For rail-to-rail CMOS, roughly what fraction of $V_{D D}$ should each margin be?

Step 1 — High-side margin. $N M_{H} = V_{O H} - V_{I H} = 1.0 - 0.58 = 0.42 V$ . Why this tool? $N M_{H}$ is the "headroom": how far a driver's clean HIGH ( $V_{O H}$ ) sits above the worst still-accepted HIGH input ( $V_{I H}$ ). Anything eaten by noise inside that gap is still read as 1.

Step 2 — Low-side margin. $N M_{L} = V_{I L} - V_{O L} = 0.42 - 0 = 0.42 V$ . Why? Mirror reasoning: how far a clean LOW output sits below the highest input still read as 0.

Step 3 — Symmetry check. $N M_{H} = N M_{L} = 0.42 V$ , and $V_{I L}, V_{I H}$ are symmetric about $0.5 = V_{D D} /2$ . Why? Equal margins are the fingerprint of a symmetric ( $k_{n} = k_{p}$ ) inverter — the same balance we sized for in Ex 5.

Verify: $N M_{H} = N M_{L} = 0.42 V = 42%$ of $V_{D D}$ — the largest possible for this rail because $V_{O H}, V_{O L}$ hit the full rails. ✓

Ex 9 — The degraded pass: NMOS as pull-up (cell C9, the "wrong" circuit)

Worked example

Statement: Suppose someone builds the pull-up from an NMOS instead of a PMOS. Input LOW, so this NMOS is meant to pass a HIGH. With $V_{D D} = 1.0$ , $V_{t n} = 0.3$ , what is the highest $V_{o u t}$ it can deliver?

Forecast: Full $1.0 V$ , or short of it?

Step 1 — Gate is tied to $V_{D D}$ (to turn it on), drain to $V_{D D}$ , output at source. As the source (output) rises, $V_{GS, n} = V_{D D} - V_{o u t}$ shrinks. Why? An NMOS pull-up self-limits: raising the output raises its own source, throttling its gate overdrive.

Step 2 — Conduction stops when $V_{GS, n} = V_{t n}$ . Set $V_{D D} - V_{o u t} = V_{t n}$ : $V_{o u t}^{ma x} = V_{D D} - V_{t n} = 1.0 - 0.3 = 0.7 V .$ Why? Below this overdrive the channel closes; the output can climb no further.

Step 3 — Interpret. Output tops out at $0.7 V$ , not $1.0$ — a degraded 1, losing exactly $V_{t n}$ . That is why the real CMOS inverter uses PMOS for pull-up (it passes a strong, full-rail 1). Why? Nails the parent's mistake-callout: device placement follows which value it passes cleanly, not raw current strength.

Verify: Loss $= V_{D D} - V_{o u t}^{ma x} = 0.3 = V_{t n}$ exactly. ✓ Confirms "NMOS makes a poor pull-up." ✓

Ex 10 — Exam twist: the transition band (cell C10)

Worked example

Statement: Hold $V_{in} = V_{M} = 0.5 V$ (symmetric inverter) statically. Are both transistors conducting? Qualitatively, what happens to the current from $V_{D D}$ to GND, and why is this only a problem during switching, not steady logic?

Forecast: Is static current zero here, like the parent claims for logic 0/1?

Step 1 — Test both devices at $V_{in} = 0.5$ . NMOS: $V_{GS, n} = 0.5 > 0.3$ → ON. PMOS: $V_{GS, p} = 0.5 - 1.0 = - 0.5 < - 0.3$ → ON. Both conduct. Why? $V_{M}$ is defined as the point where currents are equal and nonzero — by construction both are on.

Step 2 — Consequence. A direct $V_{D D} \to GND$ path exists → a short-circuit current $I_{sc}$ flows. This is the peak of the current-vs- $V_{in}$ hump. Why? Two ON series switches complete the circuit; current is momentarily nonzero — this is $P_{s h or t}$ from the parent's power split.

Step 3 — Why it's not a static-power disaster. A real input never parks at $V_{M}$ ; it sweeps through in picoseconds. Time spent in the band $\to$ small, so the energy per transition is tiny. In genuine steady logic (Ex 1, Ex 2) one device is fully OFF and $I_{sc} = 0$ . Why? Distinguishes the transient short-circuit current from the (near-zero) static leakage — the exact confusion in the parent's first mistake-box.

Verify: At $V_{in} \in {0, V_{D D}}$ one $V_{GS}$ is sub-threshold → $I_{sc} = 0$ ; only inside the band is it nonzero. ✓ Consistent with $P_{s t a t i c} \approx 0$ yet $P_{s h or t} > 0$ during edges. ✓

Recall Quick self-test (cover the answers)

At $V_{in} = 0.8$ , is the PMOS ON? ::: $V_{GS, p} = 0.8 - 1.0 = - 0.2$ ; since $- 0.2 < - 0.3$ is false, PMOS is OFF. Drop $V_{D D}$ to half; dynamic power becomes what fraction? ::: $(1/2)^{2} = 1/4$ . With $k_{n} / k_{p} = 1$ , what is $V_{M}$ ? ::: $V_{D D} /2 = 0.5 V$ . NMOS pull-up delivers at most? ::: $V_{D D} - V_{t n} = 0.7 V$ (a degraded 1).

See also: MOSFET operating regions · Propagation delay and transistor sizing · Dynamic power and clock frequency · Noise margins in digital logic · Leakage and short-channel effects · CMOS logic gates (NAND NOR)