CMOS inverter structure and operation: Exercises — Hardware deep dive

This page is a self-test ladder for the CMOS inverter. Each problem states its level — start at L1 and climb. Every solution is hidden inside a collapsible callout: try first, then reveal.

Constants used throughout (unless a problem overrides them): threshold voltages $V_{t n} = + 0.4 V$ (NMOS turns on when its gate-to-source voltage exceeds this), $V_{tp} = - 0.4 V$ (PMOS turns on when its gate is below its source by more than $0.4 V$ ). Supply $V_{D D} = 1.0 V$ .

Before we start, one picture to fix the naming so every symbol below is anchored:

Figure s01 — labelled inverter schematic. The PMOS (orange, top) has its source on $V_{D D}$ ; the NMOS (teal, bottom) has its source on GND; their drains meet at the output node $V_{o u t}$ (plum); their gates are tied together and driven by $V_{in}$ (plum). Use this picture whenever a solution mentions "source", "drain" or "gate".

Figure — CMOS inverter structure and operation

Definition Symbol cheat-sheet (everything used on this page)

$V_{D D}$ ::: the positive supply rail (the "battery +"). Here $1.0 V$ .
$GND$ ::: ground, the $0 V$ reference rail (the "battery −"). Every voltage on this page is measured relative to it.
$V_{in}$ ::: voltage on the shared gate terminal (the input wire).
$V_{o u t}$ ::: voltage on the shared drain terminal (the output wire).
$V_{GS}$ ::: gate voltage minus source voltage of one transistor. When we mean a specific transistor we add a device letter: $V_{GS, n}$ for the NMOS, $V_{GS, p}$ for the PMOS. Conduction depends on this, not on the gate voltage alone.
$V_{D S}$ ::: drain voltage minus source voltage; likewise $V_{D S, n}$ , $V_{D S, p}$ for the two devices. It decides triode-vs-saturation.
$V_{t n}, V_{tp}$ ::: threshold voltages — the "how hard do I push the gate before the switch closes" numbers.
$k_{n}, k_{p}$ ::: strength knobs, $k = μ C_{o x} (W / L)$ . Bigger $k$ = more current for the same voltage = a "stronger" switch.
$C_{L}$ ::: load capacitance the output must charge/discharge each switch.
$V_{M}$ ::: switching threshold — the input where output equals input.

Definition Three MOSFET regions you must recognise (refresher)

A MOSFET is not just ON/OFF — when ON it lives in one of two shapes (full detail in MOSFET operating regions):

Cutoff (OFF): $∣ V_{GS} ∣ < ∣ V_{t} ∣$ . The channel isn't formed → (ideally) zero current. This is what we mean by "OFF".
Triode / linear (ON, "resistor-like"): channel formed and the drain-source voltage is small ( $∣ V_{D S} ∣ < ∣ V_{GS} - V_{t} ∣$ ). The device acts like a small resistor pulling the output hard to a rail. This is the "ON" state at the flat ends of the VTC.
Saturation (ON, "current-source-like"): channel formed but $∣ V_{D S} ∣ \geq ∣ V_{GS} - V_{t} ∣$ . Current stops depending on $V_{D S}$ and becomes $I_{s a t} \approx \frac{1}{2} k (V_{GS} - V_{t})^{2}$ — a fixed current set almost entirely by the gate overdrive $(V_{GS} - V_{t})$ .

Why saturation matters for $V_{M}$ : near the switching point the output is far from either rail, so both transistors have a large $∣ V_{D S} ∣$ → both sit in saturation → both obey that clean square-law $I_{s a t}$ . That is exactly why the $V_{M}$ formula below equates two square-law currents.

Level 1 — Recognition

L1.1 — Which switch is closed?

The input is held at $V_{in} = 1.0 V$ (a solid logic HIGH). State whether NMOS and PMOS are ON or OFF, and give $V_{o u t}$ .

Recall Solution

NMOS source sits at $GND$ ( $0 V$ ), so $V_{GS, n} = V_{in} - 0 = 1.0 V$ . Since $1.0 > V_{t n} = 0.4$ , NMOS is ON (channel formed → not in cutoff). PMOS source sits at $V_{D D}$ , so $V_{GS, p} = V_{in} - V_{D D} = 1.0 - 1.0 = 0 V$ . PMOS needs $V_{GS, p} < V_{tp} = - 0.4$ ; here $0 > - 0.4$ , so PMOS is OFF (cutoff). One path only — the ON NMOS sits in triode and pulls the output all the way to ground. $V_{o u t} = 0 V$ (LOW). Inverted, as promised.

L1.2 — Read the truth table backwards

Someone measures $V_{o u t} = V_{D D}$ . What must the input have been, and which transistor was conducting?

Recall Solution

Output HIGH means the output is tied up to $V_{D D}$ — so the pull-up switch must be closed (conducting), and that switch is the PMOS. (Its partner, the pull-down NMOS, must be non-conducting, otherwise the output would be shorted between both rails.) PMOS conducts only when the input is LOW. So $V_{in} = 0$ , PMOS ON, NMOS OFF.

Level 2 — Application

L2.1 — Is the PMOS on yet?

$V_{D D} = 1.0 V$ , $V_{tp} = - 0.4 V$ . The input ramps up to $V_{in} = 0.7 V$ . Is the PMOS still conducting?

Recall Solution

$V_{GS, p} = V_{in} - V_{D D} = 0.7 - 1.0 = - 0.3 V$ . Condition to be ON: $V_{GS, p} < V_{tp}$ , i.e. $- 0.3 < - 0.4$ ? No ( $- 0.3$ is greater than $- 0.4$ ). PMOS is OFF (cutoff). The gate is not yet a full $0.4 V$ below the source, so the switch has already opened.

L2.2 — Dynamic power of a gate

A gate has $C_{L} = 20 fF$ , runs at $V_{D D} = 1.0 V$ , clock $f = 2 GHz$ , activity factor $α = 0.15$ . Find the capacitive (switching) power $P_{c a p}$ .

Recall Solution

Use $P_{c a p} = α C_{L} V_{D D}^{2} f$ (each full charge/discharge cycle dumps $C_{L} V_{D D}^{2}$ of energy into the transistors; $α$ = fraction of clocks that actually switch — see Dynamic power and clock frequency). $P_{c a p} = 0.15 \times (20 \times 1 0^{- 15}) \times (1.0)^{2} \times (2 \times 1 0^{9})$ $= 0.15 \times 20 \times 2 \times 1 0^{- 15 + 9} = 6 \times 1 0^{- 6} W = 6 μ W .$

Important caveat — this is not all of the dynamic power. True dynamic power has two pieces: $P_{d y n} = P_{c a p} (this problem) α C_{L} V_{D D}^{2} f + short-circuit current P_{s h or t} .$ During each transition the input passes through $V_{M}$ , where (as we saw in the region refresher) both transistors are momentarily ON in saturation, so a brief $V_{D D} \to GND$ current spike flows. In modern gates $P_{s h or t}$ is typically $\sim 5 - 15%$ of $P_{c a p}$ and shrinks if input edges are fast. We compute $P_{c a p}$ here because it dominates, but never say " $α C_{L} V_{D D}^{2} f$ is the dynamic power" — it is only the capacitive term.

L2.3 — Halve the supply

Take the L2.2 gate and drop $V_{D D}$ from $1.0 V$ to $0.5 V$ (keep everything else). By what factor does $P_{c a p}$ change?

Recall Solution

Only the $V_{D D}^{2}$ term changes. Ratio $= (\frac{0.5}{1.0})^{2} = 0.25$ . Power drops to one quarter ( $6 μ W \to 1.5 μ W$ ). This quadratic dependence is the reason voltage scaling beats every other power lever.

Level 3 — Analysis

L3.1 — Compute the switching threshold $V_{M}$

An inverter has $V_{D D} = 1.0 V$ , $V_{t n} = 0.4 V$ , $V_{tp} = - 0.4 V$ , and $k_{n} / k_{p} = 4$ (a deliberately unbalanced inverter). Find $V_{M}$ — and first derive the formula so you know where it comes from.

Recall Solution

Step 1 — WHY both devices are in saturation here — checked formally. At $V_{M}$ we have $V_{o u t} = V_{in} = V_{M}$ . Take our numbers and test the saturation condition $∣ V_{D S} ∣ \geq ∣ V_{GS} - V_{t} ∣$ for each device (we'll confirm $V_{M} \approx 0.467$ in Step 6, but the check works with the mid-rail estimate too):

NMOS: $V_{D S, n} = V_{o u t} - 0 = V_{M} \approx 0.467$ . Overdrive $V_{GS, n} - V_{t n} = V_{M} - 0.4 \approx 0.067$ . Since $0.467 \geq 0.067$ , NMOS is saturated. ✓
PMOS: $V_{D S, p} = V_{o u t} - V_{D D} = V_{M} - 1.0 \approx - 0.533$ , so $∣ V_{D S, p} ∣ \approx 0.533$ . Overdrive magnitude $∣ V_{GS, p} - V_{tp} ∣ = ∣ (V_{M} - 1.0) - (- 0.4) ∣ = ∣ V_{M} - 0.6∣ \approx 0.133$ . Since $0.533 \geq 0.133$ , PMOS is saturated. ✓

So both formally satisfy saturation, and both obey the square-law $I_{s a t} = \frac{1}{2} k (V_{GS} - V_{t})^{2} .$ WHY this equation and not Ohm's law? In saturation the current stops depending on $V_{D S}$ and is set by the gate overdrive squared — that is the only regime where a clean closed-form for $V_{M}$ exists.

Step 2 — write each current (with $V_{in} = V_{M}$ ). NMOS overdrive is positive already: $V_{GS, n} - V_{t n} = V_{M} - V_{t n}$ , so $I_{n} = \frac{1}{2} k_{n} (V_{M} - V_{t n})^{2} .$ PMOS needs care with signs, because $V_{GS, p}$ and $V_{tp}$ are both negative. The raw quantity is $V_{GS, p} - V_{tp} = (V_{M} - V_{D D}) - V_{tp} = (V_{M} - 1.0) - (- 0.4) = V_{M} - 0.6,$ which is negative for $V_{M} < 0.6$ . The square-law uses the magnitude of the overdrive, and squaring removes the sign, so $(V_{GS, p} - V_{tp})^{2} = (V_{M} - 0.6)^{2} = (V_{D D} + V_{tp} - V_{M})^{2},$ where the last equality just rewrites $- (V_{M} - V_{D D} - V_{tp}) = V_{D D} + V_{tp} - V_{M}$ (a positive number). Hence $I_{p} = \frac{1}{2} k_{p} (V_{D D} + V_{tp} - V_{M})^{2},$ with the bracket now guaranteed positive.

Step 3 — series constraint: the currents must be equal. NMOS and PMOS are in series, so the same current flows: $I_{n} = I_{p}$ . $\frac{1}{2} k_{n} (V_{M} - V_{t n})^{2} = \frac{1}{2} k_{p} (V_{D D} + V_{tp} - V_{M})^{2} .$

Step 4 — take the square root of both sides (both bracketed terms are positive at $V_{M}$ , so we may root them directly). To keep the algebra tidy, introduce a single ratio symbol $r \equiv k_{n} / k_{p},$ which measures "how much stronger the NMOS is than the PMOS" as a voltage-scale factor (a square root, because current $\propto k$ but voltage $\propto k$ ). Rooting Step 3 and dividing by $k_{p}$ : $k_{n} (V_{M} - V_{t n}) = k_{p} (V_{D D} + V_{tp} - V_{M}) \Rightarrow r (V_{M} - V_{t n}) = V_{D D} + V_{tp} - V_{M} .$ Step 5 — solve for $V_{M}$ : collect $V_{M}$ terms: $V_{M} (1 + r) = V_{D D} + V_{tp} + r V_{t n} \Rightarrow V_{M} = \frac{V _{D D} + V _{tp} + V _{t n} k _{n} / k _{p}}{1 + k _{n} / k _{p}} .$ This is where the mysterious $k_{n} / k_{p}$ came from — the square root in Step 4, i.e. our $r$ .

Step 6 — plug in numbers. $r = k_{n} / k_{p} = 4 = 2$ : $V_{M} = \frac{1.0 + ( - 0.4 ) + 0.4 \times 2}{1 + 2} = \frac{1.0 - 0.4 + 0.8}{3} = \frac{1.4}{3} = 0.4 \overline{6} V \approx 0.467 V .$ Because the NMOS is 4× stronger, it pulls the switch point below mid-rail ( $0.5 V$ ) — it "wins" earlier. The figure below shows this shift.

Figure s02 — VTC and the location of $V_{M}$ . The teal solid curve is the symmetric inverter ( $V_{M} = 0.5 V$ , L3.2/L3.3); the dashed orange curve is this L3.1 unbalanced inverter ( $k_{n} / k_{p} = 4$ , $V_{M} \approx 0.467 V$ ). The dotted plum line is $V_{o u t} = V_{in}$ . Each curve crosses that line at its own $V_{M}$ — that crossing is the definition of the switching threshold. Notice the orange crossing is pulled left of centre because the stronger NMOS wins the tug-of-war earlier.

L3.2 — Size for a symmetric inverter

Electron mobility is $2.5 \times$ hole mobility ( $μ_{n} = 2.5 μ_{p}$ ). You want $k_{n} = k_{p}$ so that $V_{M} = V_{D D} /2$ . With equal channel lengths $L$ and $(W / L)_{n} = 2$ , find $(W / L)_{p}$ .

Recall Solution

$k = μ C_{o x} (W / L)$ . Setting $k_{n} = k_{p}$ with the same $C_{o x}$ : $μ_{n} (W / L)_{n} = μ_{p} (W / L)_{p} \Rightarrow (W / L)_{p} = \frac{μ _{n}}{μ _{p}} (W / L)_{n} = 2.5 \times 2 = 5.$ PMOS is 2.5× wider. This "beta ratio" sizing balances pull-up and pull-down — see Propagation delay and transistor sizing.

L3.3 — Verify it lands at mid-rail

Take the L3.2 sized inverter ( $k_{n} = k_{p}$ , so $k_{n} / k_{p} = 1$ ) with $V_{D D} = 1.0$ , $V_{t n} = 0.4$ , $V_{tp} = - 0.4$ . Show $V_{M} = 0.5 V$ .

Recall Solution

$r = k_{n} / k_{p} = 1$ . $V_{M} = \frac{1.0 + ( - 0.4 ) + 0.4 \times 1}{1 + 1} = \frac{1.0 - 0.4 + 0.4}{2} = \frac{1.0}{2} = 0.5 V . ✓$ Symmetric thresholds ( $V_{t n} = - V_{tp}$ ) plus equal strengths always centre $V_{M}$ .

Level 4 — Synthesis

L4.1 — Design to a power budget

You must build a gate whose $P_{c a p} \leq 4 μ W$ . Fixed: $V_{D D} = 1.0 V$ , $f = 1 GHz$ , $α = 0.2$ . What is the largest $C_{L}$ you may drive?

Recall Solution

Rearrange $P_{c a p} = α C_{L} V_{D D}^{2} f$ for $C_{L}$ : $C_{L} = \frac{P _{c a p}}{α V _{D D}^{2} f} = \frac{4 \times 1 0 ^{- 6}}{0.2 \times 1. 0 ^{2} \times 1 \times 1 0 ^{9}} = \frac{4 \times 1 0 ^{- 6}}{2 \times 1 0 ^{8}} = 2 \times 1 0^{- 14} F = 20 fF .$ Any load up to 20 fF fits the budget.

L4.2 — Trade voltage against frequency

A design runs at $V_{D D} = 1.0 V$ , $f = 1 GHz$ . Marketing wants the same throughput per joule but at $V_{D D} = 0.8 V$ . Assuming (roughly) that max frequency scales linearly with $V_{D D}$ here, does $P_{c a p}$ go up or down, and by what factor? (Same $α, C_{L}$ .)

Recall Solution

Lowering $V_{D D}$ slows the transistors, so $f$ must drop to $f^{'} = 1 GHz \times \frac{0.8}{1.0} = 0.8 GHz$ . $\frac{P ^{'}}{P} = (\frac{V _{D D}^{'}}{V _{D D}})^{2} \cdot \frac{f ^{'}}{f} = (0.8)^{2} \times 0.8 = 0.64 \times 0.8 = 0.512.$ Power drops to ~51.2% — roughly halved. Voltage scaling is a $V_{D D}^{3}$ -ish win once you let frequency fall with it. (This is the intuition behind DVFS; contrast with Leakage and short-channel effects which fights back at low voltage.)

Level 5 — Mastery

L5.1 — Noise-margin sanity check

An ideal CMOS inverter has $V_{O H} = V_{D D} = 1.0 V$ , $V_{O L} = 0 V$ . Measurement gives the unity-slope points $V_{I L} = 0.42 V$ and $V_{I H} = 0.58 V$ . Compute both noise margins and say which logic level is better protected.

Recall Solution

$N M_{H} = V_{O H} - V_{I H} = 1.0 - 0.58 = 0.42 V .$ $N M_{L} = V_{I L} - V_{O L} = 0.42 - 0 = 0.42 V .$ Both margins are $0.42 V$ — perfectly balanced, which is exactly what a symmetric VTC ( $V_{M} = V_{D D} /2$ ) should give. Neither level is favoured. Details in Noise margins in digital logic.

L5.2 — Why an NMOS-only "inverter" is a bad idea

Suppose someone builds a pull-up from an NMOS (drain toward $V_{D D}$ , source toward the output) instead of a PMOS. With $V_{t n} = 0.4 V$ and $V_{D D} = 1.0 V$ , what is the highest output voltage this pull-up can deliver, and why is that the fatal flaw?

Recall Solution

Set up which terminal is which. As this NMOS charges the output up, current flows into the output node, so for the NMOS the output node is the source (it is the more-negative of the two ends while charging) and $V_{D D}$ is the drain. Drive the gate as hard as possible: $V_{g a t e} = V_{D D} = 1.0 V$ .

Apply the ON-condition. An NMOS keeps conducting only while $V_{GS, n} = V_{g a t e} - V_{so u r ce} > V_{t n}$ , i.e. while $V_{D D} - V_{o u t} > 0.4$ . As $V_{o u t}$ climbs, $V_{GS, n}$ shrinks. The moment $V_{o u t}$ reaches the point where $V_{D D} - V_{o u t} = V_{t n} \Rightarrow V_{o u t} = V_{D D} - V_{t n} = 1.0 - 0.4 = 0.6 V,$ we have $V_{GS, n} = V_{t n}$ exactly — the overdrive hits zero, the channel pinches off, and the transistor slides into cutoff. It cannot push charge any higher: any further rise in $V_{o u t}$ would make $V_{GS, n} < V_{t n}$ , which is OFF.

The fatal flaw. The output tops out at $V_{o u t, m a x} = 0.6 V$ , a degraded 1 — it never reaches the full $V_{D D} = 1.0 V$ that a clean logic HIGH needs. This eats the high-side noise margin and can fail to switch the next gate. That is exactly why the pull-up in real CMOS is a PMOS: with its source pinned to $V_{D D}$ , the PMOS overdrive does not collapse as the output rises, so it drives the output all the way to $V_{D D}$ — a strong 1. Device placement follows which value each device passes well, matching the parent note.

L5.3 — Full-chain reasoning

A symmetric inverter ( $V_{M} = 0.5 V$ , $V_{D D} = 1.0 V$ ) receives $V_{in} = 0.5 V$ exactly (right at $V_{M}$ ). Describe the transistor states, the output voltage, and why holding a real gate here is dangerous for power.

Recall Solution

At $V_{in} = V_{M} = 0.5 V$ : $V_{GS, n} = 0.5 > 0.4$ → NMOS ON (saturated); $V_{GS, p} = 0.5 - 1.0 = - 0.5 < - 0.4$ → PMOS ON (saturated). Both conduct in saturation. By definition of $V_{M}$ , $V_{o u t} = V_{in} = 0.5 V$ . Danger: with both transistors on there is a direct $V_{D D} \to GND$ path → large short-circuit current flows continuously (this is the $P_{s h or t}$ term from L2.2, now sustained instead of a brief spike). In normal operation this state lasts only nanoseconds during a transition; parking an input at $V_{M}$ (e.g. a slow/floating input) burns steady power. This is why inputs must be driven to full rails, not left mid-way.

Recall One-line self-check before you leave

Can you, from memory, (a) state the ON-conditions using $V_{GS}$ not the gate alone, (b) derive $V_{M}$ from equal saturation currents including the $k_{n} / k_{p}$ , (c) explain the $V_{D D}^{2}$ in $P_{c a p}$ and name the second dynamic term $P_{s h or t}$ , and (d) explain why the pull-up must be PMOS? If yes — you own the inverter.