CMOS inverter structure and operation

3.2.1 · Hardware › CMOS Circuit Design

CMOS inverter digital design ka "hydrogen atom" hai: isse poori tarah samjho aur baaki sab CMOS gates apne aap samajh aa jaenge.

YEH arrangement kyun? (Behaviour ki derivation)

Hume har input ke liye decide karna hai ki kaunsa transistor conduct karta hai. MOS conduction ke rules:

Ek MOSFET tab conduct karta hai jab $∣ V_{GS} ∣ > ∣ V_{t} ∣$ (gate-to-source voltage threshold se zyada ho).

NMOS (source GND = 0 V par): $V_{GS, n} = V_{in} - 0 = V_{in}$ Toh NMOS ON hota hai jab $V_{in} > V_{t n}$ (input HIGH).

PMOS (source $V_{D D}$ par): $V_{GS, p} = V_{in} - V_{D D}$ PMOS ON hota hai jab $V_{GS, p} < V_{tp}$ (kyunki $V_{tp} < 0$ ), yaani jab $V_{in} - V_{D D} < V_{tp}$ , yaani $V_{in}$ kaafi low ho. Toh PMOS ON hota hai jab input LOW ho.

Case-by-case truth table

$V_{in}$	NMOS	PMOS	Output path	$V_{o u t}$
0 (LOW)	OFF	ON	pull-up to $V_{D D}$	$V_{D D}$ (HIGH)
$V_{D D}$ (HIGH)	ON	OFF	pull-down to GND	0 (LOW)

Voltage Transfer Characteristic (VTC)

Paanch operating regions jab $V_{in}$ badhta hai:

$V_{in} < V_{t n}$ : NMOS OFF, PMOS ON (linear) → $V_{o u t} = V_{D D}$ .
Dono ON, NMOS saturated → output girna shuru hota hai.
Switching point $V_{M}$ : dono saturation mein, teezi se girta hai.
Dono ON, PMOS saturated → output GND ke paas.
$V_{in} > V_{D D} + V_{tp}$ : NMOS ON (linear), PMOS OFF → $V_{o u t} = 0$ .

Power dissipation (CMOS kyun jeetta hai)

Dynamic (switching) power — ise derive karte hain. Har baar output $0 \to V_{D D}$ jaata hai, load capacitor $C_{L}$ energy store karta hai $\frac{1}{2} C_{L} V_{D D}^{2}$ , aur utni hi energy PMOS mein heat ke roop mein dissipate hoti hai. Neeche jaate waqt $\frac{1}{2} C_{L} V_{D D}^{2}$ NMOS mein dissipate hoti hai. Toh har full cycle mein $C_{L} V_{D D}^{2}$ dissipate hoti hai. Agar yeh $f$ baar per second hota hai switching probability $α$ ke saath:

Static power ≈ 0 (ideal) kyunki ek transistor hamesha OFF rehta hai, DC path block karta hai. (Real chips mein leakage hoti hai, lekin classically CMOS static power negligible hai.)

Noise margins (digital robust kyun hai)

Common mistakes

Flashcards

CMOS mein "complementary" ka matlab kya hai?

Isme NMOS aur PMOS ka ek matched pair use hota hai jo opposite gate conditions par ON hote hain.

CMOS inverter mein kaunsa transistor pull-up hai aur kaunsa pull-down?

PMOS = pull-up (to

V_{D D}

), NMOS = pull-down (to GND).

Jab input HIGH ho, kaunsa transistor conduct karta hai aur output kya hota hai?

NMOS ON, PMOS OFF → output LOW.

CMOS mein static power ~0 kyun hoti hai?

Steady state mein ek transistor hamesha OFF rehta hai,

V_{D D}

se GND tak DC path todta hai.

Dynamic power formula batao aur

V_{D D}^{2}

explain karo.

P = α C_{L} V_{D D}^{2} f

; har event ki energy ∝ charge(

V_{D D}

)×voltage(

V_{D D}

Switching threshold

V_{M}

kya hai?

Woh

V_{in}

jahan

V_{o u t} = V_{in}

ho; dono transistors saturated; ideally

V_{D D} /2

PMOS ko NMOS se 2–3× wider kyun banate hain?

Hole mobility electron mobility se 2–3× kam hai; PMOS ko wide karne se

k_{n} = k_{p}

equal hota hai jo symmetric VTC aur equal rise/fall ke liye zaroori hai.

NMOS conduct karne ki condition kya hai?

V_{GS, n} = V_{in} > V_{t n}

PMOS conduct karne ki condition (

V_{tp} < 0

ke saath)?

V_{in} - V_{D D} < V_{tp}

, yaani input kaafi low ho.

N M_{H}

kya hai?

N M_{H} = V_{O H} - V_{I H}

, high-side noise margin.

NMOS poor pull-up kyun hai?

Yeh degraded HIGH pass karta hai (output sirf

V_{D D} - V_{t n}

tak pahunchta hai).

Recall Feynman: ek 12-saal ke bacche ko explain karo

Socho ek light bulb hai jisme do switches hain. Ek switch bulb ko battery se connect karta hai (upar), doosra ground se (neeche). Dono switches ek hi button se flip hote hain. Trick yeh hai: switches opposite hain — jab ek close hota hai, doosra open ho jaata hai. Button dabao (input = 1) aur bulb-wire ground se connect ho jaata hai → output = 0. Chodo (input = 0) aur yeh battery se connect ho jaata hai → output = 1. Kyunki kabhi aisa nahi hota ki dono zyada der tak closed hon, battery waste nahi hoti — isliye tumhara phone cool rehta hai aur battery zyada chalti hai. Yeh hamesha button ka ulta deta hai: isliye hum ise inverter kehte hain.

Connections

CMOS logic gates (NAND NOR) — inhi do devices ke series/parallel networks se banate hain.
MOSFET operating regions — VTC derivation mein cutoff/triode/saturation use hota hai.
Dynamic power and clock frequency — $α C_{L} V_{D D}^{2} f$ scaling.
Propagation delay and transistor sizing — $k_{n} = k_{p}$ rise/fall balance kyun karta hai.
Noise margins in digital logic — full-rail swing ka faayda.
Leakage and short-channel effects — modern nodes mein "static power ≈ 0" kahan fail hota hai.

The Big Picture

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