Pass-transistor logic: Question bank — Hardware deep dive

Before you start, keep the one core fact in view:

Recall The single sentence everything here tests

An nMOS conducts only while == $V_{GS} = V_{G} - V_{S} > V_{t n}$ ==, and when it passes a signal the moving node is its source $V_{S}$ . So the device's ON-ness changes as the output moves. That one coupling explains strong-0/weak-1, body effect, and every leakage trap below.

True or false — justify

Tying an nMOS gate to

V_{D D}

makes it pass a full clean '1'.

False. ON-ness is

V_{GS} = V_{D D} - V_{o u t}

; as

V_{o u t}

climbs, this shrinks and the channel cuts off at

V_{o u t} = V_{D D} - V_{t n}

— a threshold below the rail.

An nMOS passes a perfect '0' with no degradation.

True. Discharging, the source falls to

0

, so

V_{GS} = V_{D D} - 0 = V_{D D} ≫ V_{t n}

; the device stays strongly ON all the way down.

A pMOS pass transistor has the opposite problem: strong '1', weak '0'.

True. By the mirror argument it stays ON while

V_{S G} > ∣ V_{tp} ∣

; passing a '0' its channel cuts off once

V_{o u t}

falls only to

∣ V_{tp} ∣

, leaving a weak '0'.

The threshold drop

V_{D D} - V_{t n}

is the worst case for the weak '1'.

False. Body effect makes it worse: here

V_{S B} = V_{o u t}

is large, which raises

V_{t n}

above

V_{t n 0}

, so the actual '1' sits below

V_{D D} - V_{t n 0}

A transmission gate passes both rails full-swing.

True. The nMOS handles the low half strongly and the parallel pMOS handles the high half strongly, so between them every voltage rail-to-rail has one device strongly ON.

A PTL 2:1 MUX needs zero inverters.

False. You need one inverter to generate

\overset{ˉ}{S}

so that exactly one of the two pass transistors is ON at a time; the two pass transistors alone can't produce complementary steering.

PTL always saves power.

False. A degraded '1' feeding a following CMOS gate can leave its pMOS partly on → static leakage, potentially costing more than the transistors saved.

A pass transistor provides gain to restore signal strength.

False. It only conducts an existing voltage; it has no pull-up/pull-down to a rail of its own, so it cannot amplify — long chains only degrade further.

Spot the error

"To fix the weak '1' from an nMOS, just make

V_{D D}

larger."

Error. Raising

V_{D D}

raises the ceiling and the input, so the output still stops a full

V_{t n}

short of the (now higher) rail — the gap stays. You must add a pMOS path or a restoring pMOS.

"Since

V_{G} = V_{D D}

is the maximum voltage, the nMOS is 'fully on' for any passed signal."

Error. "Fully on" depends on

V_{GS}

, not

V_{G}

alone. Passing a '1', the source (output) rises, so

V_{GS}

falls even though

V_{G}

is fixed at the max.

"A transmission gate uses two nMOS in parallel to be twice as strong."

Error. It uses one nMOS and one pMOS in parallel with complementary gates; two nMOS would both suffer the same weak-'1' problem, fixing nothing.

"Feeding a

1.4

V weak-'1' into an inverter with

V_{tp} = - 0.4

V_{D D} = 1.8

V is fine because

1.4

V is a logic high."

Error. The pMOS needs

V_{S G} > 0.4

i.e. gate below

1.8 - 0.4 = 1.4

V; the input is exactly

1.4

V, so the pMOS sits right at threshold — barely off and leaking.

"nMOS passes strong '1', pMOS passes strong '0'."

Error. Backwards. nMOS = strong 0 / weak 1; pMOS = strong 1 / weak 0. Mnemonic: N passes low, P passes high.

"The level-restoring pMOS is placed on the signal path in series with the pass transistors."

Error. It's a feedback device from

V_{D D}

to the degraded node, triggered by the following inverter's output; it pulls the weak node up in parallel, not in the pass path.

Why questions

Why does the passed node act as the transistor's source rather than its drain when passing a '1'?

For an nMOS the source is the lower-potential terminal; while charging a '1', conventional current flows from the

V_{D D}

input into the output, so the output is the low side — the source — and its rising voltage directly shrinks

V_{GS}

Why is the weak-'1' problem invisible if you only test passing a '0'?

Passing '0' the source goes to ground, keeping

V_{GS} = V_{D D}

huge, so the device works perfectly — the failure only appears on the opposite rail, which a lazy test never exercises.

Why does XOR map naturally onto pass-transistor logic?

Y = \overset{ˉ}{B} A + B \overset{ˉ}{A}

is a MUX that routes the variables $A$ and $\overset{ˉ}{A}$ themselves as data; PTL can pass variables (not just rails), so XOR collapses into a tiny 2-input steering network.

Why do long chains of series pass transistors get slow?

Each pass transistor adds channel resistance and node capacitance; in series they form a growing RC ladder with no intermediate drive, so the delay accumulates faster than a buffered chain.

Why does a transmission gate need a complemented control signal?

The nMOS turns on with a high gate and the pMOS turns on with a low gate; to switch both on together you must drive them with opposite (complementary) control voltages.

Why does static CMOS never suffer the threshold-drop problem?

In static CMOS the output node is pulled to a rail through a device whose source is tied to that rail (not to the moving output), so

V_{GS}

stays large all the way — the output reaches the full rail.

Edge cases

What voltage does a single nMOS pass when its gate is at

V_{D D}

and the input is

0

A clean

0

V — passing a '0' keeps

V_{GS} = V_{D D}

, so the device stays strongly ON down to ground with no degradation.

What happens at the exact instant

V_{o u t} = V_{D D} - V_{t n}

while passing a '1'?

V_{GS}

has fallen to exactly

V_{t n}

, the channel is at the edge of cutoff, conduction essentially stops, and charging halts — this defines the maximum deliverable '1'.

V_{t n}

were somehow

0

, could a plain nMOS pass a full '1'?

Yes — the cutoff condition

V_{o u t} = V_{D D} - V_{t n}

would give

V_{o u t} = V_{D D}

; the whole weak-'1' problem is the nonzero threshold.

Both select lines of a PTL MUX accidentally go high at once — what happens?

Both pass transistors turn on, connecting inputs

A

and

B

directly through the channels; if they differ you get contention (a short) and an indeterminate, current-wasting output.

What is the output level if you cascade two nMOS pass transistors (drain of one to source of next), both gates at

V_{D D}

, passing a '1'?

Still limited by one threshold drop — the first stage caps at

V_{D D} - V_{t n}

, and that already-degraded level becomes the second stage's gate-relative input, so it cannot recover; it stays weak (and body effect may worsen it).

What does a pMOS pass transistor output when trying to pass a '0' (gate at

0

V, input

0

V)?

A weak '0': it stops conducting once the output falls only to

∣ V_{tp} ∣

above ground, leaving the low level a threshold above true

0

At the degraded '1' node, is the following inverter's nMOS also affected?

Its nMOS turns on even harder (bigger gate-source drive), so the output still goes low correctly; the trouble is only the pMOS not fully turning off, which causes leakage — not a logic error.

Connections

CMOS Inverter — the load whose pMOS reveals weak-'1' leakage
Transmission Gate — the rail-to-rail fix
Static CMOS Logic — the contrast case with no threshold drop
Threshold Voltage & Body Effect — origin of the drop and its worsening
Multiplexers — where these traps show up in real datapaths
Dynamic Power vs Static Leakage — the cost of degraded levels