Pass-transistor logic: Visual walkthrough — Hardware deep dive

Every symbol is earned before it is used. We start from "what is a transistor doing" and end at the boxed formula.

Step 1 — What the pieces are (before any equation)

WHAT. We have three things on the table:

A voltage — think of it as how hard water is being pushed at a point. We measure it in volts (V). The name for the biggest voltage in our chip is $V_{D D}$ (the "supply rail", the ceiling). The bottom is GND = 0 V (the floor).
An nMOS transistor — a switch with three touch-points: two are the ends of the water pipe (called source and drain), and one is the handle that opens or closes the pipe (called the gate).
An output node — a little bucket (a wire with some capacitance) that starts empty (0 V) and that we are trying to fill up to '1'.

WHY name them now. Every later equation is a statement about the difference between two of these touch-points. If you don't know which point is which, the algebra is just letters. Look at the picture and burn the three terminals into memory.

PICTURE.

Step 2 — The one rule that governs everything: $V_{GS} > V_{t n}$

WHAT. An nMOS pipe is open (lets current through) only when the handle is raised enough above the source end. Written as a rule:

$gate voltage minus source voltage V_{GS} > the "threshold" — the minimum push needed V_{t n}$

Term by term, right where it lives:

$V_{GS} = V_{G} - V_{S}$ — the gate voltage measured relative to the source. Not the raw gate voltage — the difference. This is the whole trick.
$V_{t n}$ — the threshold voltage, a fixed property of the transistor (e.g. 0.4 V). Below it the channel simply does not form; the pipe is a solid wall.

WHY this rule and not "gate is high so it's on". The physics of the channel cares about the field between gate and the nearest conducting layer — and that layer sits at the source potential. So the transistor never sees $V_{G}$ alone; it always sees $V_{G} - V_{S}$ . This single fact is the seed of the weak '1'. (For the deeper origin of $V_{t n}$ , see Threshold Voltage & Body Effect.)

PICTURE.

Recall

What does "ON" actually depend on? ::: The difference $V_{GS} = V_{G} - V_{S}$ , not the raw gate voltage.

Step 3 — Which end is the "source"? (the sign trap that makes '1' hard)

WHAT. For an nMOS, the source is whichever pipe-end sits at the lower voltage. Current (conventional) flows from high to low, and the low end is labelled $S$ .

Now split into the two jobs a pass transistor can do:

Job	Input applied at	Bucket $V_{o u t}$	Which end is source?
Pass a '0' (empty the bucket)	0 V	starts high, falls to 0	the input end (0 V)
Pass a '1' (fill the bucket)	$V_{D D}$	starts at 0, rises	the output end ( $V_{o u t}$ )

WHY this matters enormously. When we pass a '1', the output node itself becomes the source. So as the bucket fills, $V_{S} = V_{o u t}$ climbs. Watch what that does to the rule from Step 2: $V_{GS} = V_{G} - V_{S} = V_{D D} - V_{o u t} .$ The thing that keeps the switch open is shrinking as we succeed at filling. That is the trap.

PICTURE.

Step 4 — Watch the budget drain (passing a '1')

WHAT. Set $V_{G} = V_{D D}$ and feed $V_{D D}$ into the input. Track two quantities as the bucket fills from 0 upward:

$V_{o u t}$ — climbing (good, we want a '1'),
$V_{GS} = V_{D D} - V_{o u t}$ — falling (bad, this is what keeps us open).

WHY frame it as a "budget". Think of $V_{D D}$ as a budget you spend on staying open. Every volt the output rises is a volt taken out of $V_{GS}$ . You keep charging only while there's still more than $V_{t n}$ left in the budget.

Numbers make it vivid (from Worked Example 3, $V_{D D} = 1.8$ , $V_{t n} = 0.4$ ):

$V_{o u t}$ (V)	$V_{GS} = 1.8 - V_{o u t}$ (V)	still $> V_{t n} = 0.4$ ?
0.0	1.8	yes — charging hard
1.0	0.8	yes — slowing
1.4	0.4	exactly at threshold — STOP
1.5	0.3	no — pipe already shut

PICTURE.

Step 5 — The cut-off point: derive $V_{o u t, m a x} = V_{D D} - V_{t n}$

WHAT. The switch shuts the instant the budget hits exactly the threshold: $V_{GS} = V_{t n} .$ Substitute $V_{GS} = V_{D D} - V_{o u t}$ from Step 3: $shrinking budget V_{D D} - V_{o u t} = minimum to stay open V_{t n} .$ Solve for the output at that frozen moment: $V_{o u t, m a x} = V_{D D} - V_{t n}$

Term by term:

$V_{D D}$ — how high we wished to go (the input, the ceiling).
$- V_{t n}$ — the toll the transistor keeps for itself; it never lets $V_{GS}$ fall below $V_{t n}$ , so it never lets the output rise the last $V_{t n}$ volts.
$V_{o u t, m a x}$ — the frozen final voltage: a "1" that falls short of the rail by one threshold. This is the threshold drop.

WHY this is the answer and not something else. Beyond this point $V_{GS} < V_{t n}$ , so by Step 2 there is no channel — zero current — so $V_{o u t}$ cannot rise any further. The system is stuck. $V_{D D} - V_{t n}$ is a hard ceiling.

PICTURE.

Step 6 — Body effect makes it worse (the toll grows)

WHAT. We assumed $V_{t n}$ was a constant. It isn't. When the source is lifted above the body (substrate), the threshold rises: $V_{t n} = V_{t n 0} + γ (2 ϕ_{F} + V_{S B} - 2 ϕ_{F}) .$

$V_{t n 0}$ — the threshold when source and body are at the same voltage (the "base" toll).
$V_{S B} = V_{S} - V_{b o d y}$ — source-to-body voltage. Here $V_{S} = V_{o u t}$ is large, so $V_{S B}$ is large.
$γ$ (gamma) — the "body-effect coefficient", how strongly the substrate fights back.
$ϕ_{F}$ (phi-F) — a material constant of the silicon (a fixed number here).

WHY it matters. Because $V_{S B} = V_{o u t}$ is exactly the thing that's large when passing a '1', the toll $V_{t n}$ grows right when it hurts most. So the real ceiling is $V_{o u t, m a x} = V_{D D} - V_{t n} (V_{o u t}) < V_{D D} - V_{t n 0} .$ The weak '1' is even weaker than the simple formula predicts. (Full treatment: Threshold Voltage & Body Effect.)

PICTURE.

Recall

Direction of the body-effect correction? ::: It raises $V_{t n}$ (positive term), lowering the passed '1' further below $V_{D D} - V_{t n 0}$ .

Step 7 — The mirror case: why the '0' is perfect (and the pMOS)

WHAT. Run the whole argument with the bucket emptying toward 0. Now (Step 3) the source is the input end at 0 V, so $V_{S} = 0$ and $V_{GS} = V_{D D} - 0 = V_{D D} ≫ V_{t n} .$ The budget is full the entire way down — the switch never comes close to shutting. The output reaches a clean, full 0 V. Strong 0.

By the exact mirror physics, a pMOS (which turns on when the gate is below the source by $∣ V_{tp} ∣$ ) passes a strong '1' but a weak '0' — it stops when the falling output reaches $∣ V_{tp} ∣$ and cannot go lower.

$nMOS: strong 0, weak 1 pMOS: strong 1, weak 0$

This complementary pairing is exactly why the Transmission Gate (nMOS ∥ pMOS) passes both rails perfectly.

PICTURE.

The one-picture summary

The whole derivation in one frame: gate held at $V_{D D}$ (flat line), output climbing but stalling at $V_{D D} - V_{t n}$ (with the body-effect version stalling even lower), the shrinking budget $V_{GS}$ meeting the threshold line, and the mirrored '0' sliding cleanly to the floor.

Recall Feynman: the whole walkthrough in plain words

A transistor is a valve, and its handle only "feels" how far it's raised above the near end of the pipe. Emptying a tank is easy: the near end is at the floor, so the handle stays fully raised the whole time — you get a perfect empty (strong 0). Filling a tank is the trap: the near end is the water level you're raising, so every bit you fill lifts the near end and lowers how far the handle is above it. When that gap shrinks to the valve's minimum ( $V_{t n}$ ), the valve snaps shut — and it does this a full threshold before the tank is full. So an nMOS fills only up to $V_{D D} - V_{t n}$ : a weak '1'. Worse, the silicon's body pushes the threshold higher exactly when the level is high, so it stalls even lower. The cure is a second, opposite valve — a pMOS, great at filling — placed alongside: together they empty and fill perfectly. That pair is the transmission gate.

Connections

Parent: Pass-transistor logic — where this result is used
Threshold Voltage & Body Effect — the origin of $V_{t n}$ and the Step 6 correction
Transmission Gate — the fix built from Step 7's complementary pairing
CMOS Inverter — the load that turns a weak '1' into real leakage
Static CMOS Logic — the contrast: rails pulled, not signals steered
Multiplexers — the killer app of this whole idea
Dynamic Power vs Static Leakage — the cost of the degraded '1'