Pass-transistor logic: Worked examples — Hardware deep dive

This deep dive is the practice arena for Pass-transistor logic. The parent note told you the one central fact — nMOS passes strong 0 / weak 1, and the mirror fact for pMOS. Here we hunt down every case where that fact bites, helps, or hides: which input, which device, which rail, and what number comes out.

Before we start, a few plain-word reminders so nobody is lost from line one.

Definition The voltages and symbols we keep using

$V_{D D}$ — the top power rail, the highest voltage a wire can reach. Think "full tank." We use $V_{D D} = 1.8 V$ everywhere below unless told otherwise.
GND (0 V) — the bottom rail, "empty tank."
$V_{G}, V_{S}$ — the voltages at the gate (control) and source terminals of a transistor.
$V_{GS} = V_{G} - V_{S}$ — gate minus source. For an nMOS, this single number decides ON/OFF.
$V_{S G} = V_{S} - V_{G}$ — the reverse difference, source minus gate. For a pMOS, this is the number that decides ON/OFF (a pMOS wants its source pulled above its gate). We define it now so it is never used unearned.
$V_{t n}$ — the threshold voltage of an nMOS: the minimum $V_{GS}$ needed before the channel opens. If $V_{GS} < V_{t n}$ , the switch is shut.
$V_{t n 0}$ — the nominal value of $V_{t n}$ when there is no body effect (source and body at the same potential). Throughout, unless we explicitly invoke the body effect (only in Example 6), we assume $V_{t n} = V_{t n 0} = 0.4 V$ — i.e. we ignore the small rise in threshold. Example 6 is the one place where $V_{t n}$ grows above $V_{t n 0}$ .
$∣ V_{tp} ∣ = 0.4 V$ — the magnitude of the pMOS threshold (pMOS thresholds are negative; we use the magnitude).

Recall Which terminal is the "source" of a pass transistor?

The source is whichever source/drain terminal is at the lower potential for an nMOS (current flows in at drain, out at source). When passing a 1 the rising output node is the source; when passing a 0 the low output node is the source. This swap is the whole reason the two cases behave differently. ::: The lower-voltage terminal; it moves depending on which way charge flows.

The scenario matrix

Every question PTL can throw at you is one cell of this grid. We cross which device with which logic value we're trying to pass, then add the degenerate / limiting / real-world cells.

Cell	Situation	What we expect	Example
A	nMOS passing 0	strong, clean 0 V	Ex 1
B	nMOS passing 1	weak, stops at $V_{D D} - V_{t n}$	Ex 2
C	pMOS passing 1	strong, clean $V_{D D}$	Ex 3
D	pMOS passing 0	weak, stops at $∣ V_{tp} ∣$	Ex 3
E	Both (transmission gate)	rail-to-rail, both clean	Ex 4
F	Degraded 1 into next inverter	leakage / static power	Ex 5
G	Body-effect limit (worse than nominal)	1 even lower than $V_{D D} - V_{t n 0}$	Ex 6
H	Real-world word problem (2:1 MUX datapath)	pick correct input, watch level	Ex 7
I	Exam twist: series chain of pass transistors	only ONE threshold drop, but slow	Ex 8
J	Zero / degenerate: gate OFF, or $V_{D D}$ near $V_{t n}$	node floats / cannot pass a 1 at all	Ex 9

We now walk all ten cells. Grab the figures — the geometry of the shrinking $V_{GS}$ budget carries the argument.

Example 1 — nMOS passing a 0 (cell A)

Forecast: Guess before reading — will it stop short of 0, like the weak-1 case does short of $V_{D D}$ ? Write down your guess.

Read the figure first. The dashed lavender line is $V_{GS}$ ; notice it sits flat at $1.8 V$ the whole way. The coral curve is $V_{o u t}$ sliding down to 0. The mint arrow points to where the output lands — hard against 0 V, never stalling.

Identify the source. Current flows out of the output node (it's dumping charge into the 0 V input), so the output node is the higher side and the 0 V input is the source. Why this step? ON/OFF depends on $V_{GS} = V_{G} - V_{S}$ , and $V_{S}$ is whichever terminal is lower — here the fixed 0 V input.
Write the budget. $V_{GS} = V_{G} - V_{S} = 1.8 - 0 = 1.8 V$ . Why this step? This is our "how open is the valve" number — the flat dashed line in the figure.
Compare to threshold. $1.8 V ≫ V_{t n} = 0.4 V$ , and $V_{S}$ stays pinned at 0 the whole time, so $V_{GS}$ never shrinks (the dashed line never dips toward the dotted $V_{t n}$ line). Why this step? The source doesn't move (it's held at 0), so nothing eats the budget — unlike the passing-1 case.
Conclusion. The channel stays strongly ON all the way down. $V_{o u t} \to 0 V$ , a perfect 0.

Verify: $V_{GS}$ at the very end is $1.8 - 0 = 1.8 V$ , still far above $0.4 V$ → device is on → node fully discharges. Units: all volts, consistent. ✓ (This confirms parent claim: nMOS = strong 0.)

Example 2 — nMOS passing a 1 (cell B)

Forecast: Will it reach $1.8 V$ ? Guess a number.

Read the figure first. The coral curve is $V_{o u t}$ climbing, but watch the dashed lavender line: $V_{GS} = 1.8 - V_{o u t}$ falls as the output rises. Where the dashed line touches the dotted $V_{t n}$ level, the coral curve flattens — that flat ceiling, marked "weak 1 stalls at 1.4 V", is our answer, well below the mint $V_{D D}$ line.

Identify the source. Charge flows into the output node, so the output is now the lower side — the output node is the source. Why this step? The source has swapped compared to Example 1; that swap is the entire drama.
Write the shrinking budget. As the output rises, $V_{S} = V_{o u t}$ rises, so $V_{GS} = 1.8 - V_{o u t}$ falls (the descending dashed line). Why this step? The very thing we're building (a high output) eats into the voltage that keeps the switch open.
Find the cut-off point. Conduction stops when $V_{GS} = V_{t n}$ : $1.8 - V_{o u t} = 0.4 \Rightarrow V_{o u t, m a x} = 1.4 V$ . Why this step? Below $V_{GS} = V_{t n}$ there is no channel, so charging simply halts (where the two dashed/dotted lines meet in the figure).
Conclusion. The 1 is weak: it stalls at $1.4 V$ , a full $V_{t n} = 0.4 V$ below the rail.

Verify: At $V_{o u t} = 1.4$ , $V_{GS} = 1.8 - 1.4 = 0.4 = V_{t n}$ → exactly at cut-off, consistent. Any higher and $V_{GS} < V_{t n}$ (impossible to reach). ✓

Example 3 — pMOS: strong 1, weak 0 (cells C & D)

Forecast: pMOS is the mirror of nMOS. Which value comes out clean, which stalls?

pMOS ON condition. A pMOS conducts while $V_{S G} = V_{S} - V_{G} > ∣ V_{tp} ∣$ — recall from the definitions that $V_{S G}$ is source-minus-gate, the reverse of the nMOS $V_{GS}$ . Its source is the higher-voltage source/drain terminal. Why this step? pMOS is the p-type mirror: it likes to pull up, and its source is the high side.
(a) Passing a 1. As output rises toward $1.8$ , the output is the high side = source, so $V_{S} = V_{o u t}$ , gate $V_{G} = 0$ : $V_{S G} = V_{o u t} - 0 = V_{o u t}$ . This grows as $V_{o u t}$ rises, so the switch stays strongly ON right up to $1.8 V$ . Clean 1. Why this step? Rising output increases the pMOS budget — opposite of the nMOS case.
(b) Passing a 0. Now the input ( $0$ ) is the source's low side; the output discharging becomes... let's track it. When output has fallen to some $V_{o u t}$ , the higher terminal is the output → source, $V_{S} = V_{o u t}$ , $V_{S G} = V_{o u t} - 0 = V_{o u t}$ . Conduction stops when $V_{S G} = ∣ V_{tp} ∣$ : $V_{o u t} = 0.4 V$ . Weak 0 — stalls at $0.4 V$ . Why this step? As output falls, the pMOS budget shrinks; below $∣ V_{tp} ∣$ it shuts off short of 0.

Verify:

(a) clean 1 $= 1.8 V$ . ✓
(b) weak 0 $= ∣ V_{tp} ∣ = 0.4 V$ . ✓ Mirror of nMOS ( $V_{D D} - V_{t n} = 1.4$ ; here $0 + ∣ V_{tp} ∣ = 0.4$ ). Both stall one threshold from the bad rail.

Example 4 — Transmission gate: rail-to-rail (cell E)

Forecast: Which transistor rescues which half?

Read the figure first. The horizontal axis is the output node voltage from 0 to $1.8$ V. The mint band shows where the nMOS is strong (0 up to $1.4$ V); the lavender band shows where the pMOS is strong ( $0.4$ up to $1.8$ V). Notice they overlap in the middle and, crucially, together cover the entire range — the coral arrow marks the overlap where both conduct.

Passing a 1. From Ex 2 the nMOS stalls at $1.4$ (right edge of the mint band) — but from Ex 3(a) the pMOS is still strongly ON above $1.4$ (the lavender band continues to $1.8$ , its budget $V_{S G} = V_{o u t}$ keeps growing). So the pMOS carries the output the rest of the way to $1.8 V$ . Why this step? Whenever the nMOS gives up, the pMOS is fresh — they hand off at $1.4$ V, where the two bands overlap.
Passing a 0. From Ex 1 the nMOS is strong to $0$ (the mint band reaches the left edge). The pMOS quit at $0.4$ (left edge of lavender band), but the nMOS takes it down cleanly. Why this step? Symmetric hand-off: nMOS finishes the low half.
Conclusion. Together: full-swing $0 V$ to $1.8 V$ (rail-to-rail), at the cost of 2 transistors + a complemented control.

Verify: High output $= max (1.4, 1.8) = 1.8$ ✓; low output $= min (0.0, 0.4) = 0.0$ ✓. Each rail is served by its strong device.

Example 5 — Degraded 1 into a CMOS inverter (cell F)

Forecast: We want the pMOS fully off (so no leakage). Guess: comfortably off, or barely off?

pMOS off condition. The inverter's pMOS turns off when its $V_{S G} = V_{D D} - V_{in} \leq ∣ V_{tp} ∣$ . Why this step? For a clean logic 1 in, the pull-up pMOS must be shut so the output goes cleanly to 0.
Plug in. $V_{S G} = 1.8 - 1.4 = 0.4 V = ∣ V_{tp} ∣$ . Why this step? This is exactly the threshold — the pMOS is right on the boundary.
Interpret. At $V_{S G} = ∣ V_{tp} ∣$ the pMOS is barely off — sub-threshold current still trickles. This is static leakage: wasted power with no switching. Why this step? "Off at threshold" is not "off with margin"; real transistors leak here.
Fix. Restore the level (transmission gate or feedback pMOS) so the inverter sees a full $1.8 V$ , giving $V_{S G} = 0$ → truly off.

Verify: $V_{S G} - ∣ V_{tp} ∣ = 0.4 - 0.4 = 0.0 V$ margin — zero, i.e. borderline leaking. A restored $1.8 V$ input gives $V_{S G} = 0 < 0.4$ → margin $0.4 V$ , safely off. ✓

Example 6 — Body effect makes it worse (cell G)

Here we finally drop the "ignore body effect" assumption. First, the physics behind the extra symbols.

Definition Body effect, in plain words

Every MOSFET sits in a silicon "body." Normally we imagine source and body at the same voltage. But a pass transistor's source (the output node) can float high above the body, and that voltage difference $V_{S B}$ (source-to-body) makes the channel harder to form — so the threshold $V_{t n}$ rises above its nominal $V_{t n 0}$ . The size of the rise is set by two material constants:

$γ$ — the body-effect coefficient, units $V$ (so that $γ volts$ comes out in volts). Here $γ = 0.4 V$ .
$ϕ_{F}$ — the Fermi potential of the doped silicon, a fixed material voltage (here $ϕ_{F} = 0.35 V$ , so the combination $2 ϕ_{F} = 0.7 V$ ). It measures how heavily the body is doped. You do not derive it; the fab gives it to you.

$V_{t n} = V_{t n 0} + γ (2 ϕ_{F} + V_{S B} - 2 ϕ_{F})$

Forecast: We know the no-body answer is $1.4 V$ . Body effect raises $V_{t n}$ , so the answer should be lower. Guess a number.

Body-effect threshold. $V_{t n} = V_{t n 0} + γ (2 ϕ_{F} + V_{S B} - 2 ϕ_{F})$ . Why this step? When the source (our output) sits high above the body, the channel needs more gate push — $V_{t n}$ grows above $V_{t n 0}$ .
First estimate of $V_{S B}$ . Use the no-body answer $V_{o u t} \approx 1.4$ as $V_{S B}$ . Then $V_{t n} = 0.4 + 0.4 (0.7 + 1.4 - 0.7) = 0.4 + 0.4 (2.1 - 0.7)$ . Why this step? We plug a good starting guess to see how much $V_{t n}$ inflates.
Numbers. $2.1 = 1.4491$ , $0.7 = 0.8367$ ; difference $= 0.6124$ ; $\times 0.4 = 0.2450$ ; so $V_{t n} \approx 0.645 V$ . Why this step? Threshold jumped from $0.4$ ( $V_{t n 0}$ ) to $\sim 0.65 V$ .
New weak 1. $V_{o u t, m a x} = V_{D D} - V_{t n} = 1.8 - 0.645 = 1.155 V$ . Why this step? A bigger threshold means the switch shuts even earlier — the 1 is now only $\sim 1.16 V$ , well below $1.4$ .

Verify: $V_{t n} = 0.4 + 0.4 (2.1 - 0.7) \approx 0.6450$ ; $1.8 - 0.6450 \approx 1.155 V < 1.4 V$ . ✓ Body effect confirmed to worsen the 1. (A self-consistent solve with $V_{S B} = V_{o u t}$ would land slightly higher than $1.155$ ; one iteration already shows the direction and rough size.)

Example 7 — Real-world: 2:1 MUX datapath (cell H)

Forecast: $S = 1$ selects $A$ . So $Y$ should be a 1 — but how good a 1?

Which path is ON? $S = 1$ → the $A$ -path nMOS (gate $= S = V_{D D}$ ) is ON; the $B$ -path (gate $= \overset{ˉ}{S} = 0$ ) is OFF. Why this step? Exactly one select line is high, steering exactly one input to $Y$ . That's the whole point of the MUX.
Value passed. The ON nMOS passes $A = 1.8$ , a 1 → from Ex 2 it degrades to $V_{D D} - V_{t n} = 1.4 V$ . Why this step? Passing a 1 through a lone nMOS always costs a threshold.
Drive the next stage? From Ex 5, $1.4 V$ leaves the following inverter's pMOS at threshold → leakage. Why this step? In a real datapath, $Y$ feeds another gate; the weak 1 propagates the problem.
Fix in context. Replace each nMOS with a transmission gate, or add a restoring pMOS after $Y$ 's inverter → $Y$ becomes a full $1.8 V$ .

Verify: With $S = 1, A = 1, B = 0$ : $Y = 1 \cdot 1 + 0 \cdot 0 = 1$ logically ✓; electrically $= 1.4 V$ (degraded) ✓. Transistor count for the steering core $= 2$ ✓.

Example 8 — Exam twist: a series chain of pass transistors (cell I)

Forecast: Does each series device really cost its own $V_{t n}$ ?

Where does cut-off happen? Only the last node in the chain rises to become a floating high output; the intermediate nodes are pulled by the same source and settle. The final node stops when its driving transistor hits $V_{GS} = V_{t n}$ . Why this step? A threshold drop is charged once, at the node that can no longer be pushed — not once per device.
Correct answer (ignoring body effect). The far node reaches $V_{o u t, m a x} = V_{D D} - V_{t n} = 1.8 - 0.4 = 1.4 V$ , a single threshold drop, not three. Why this step? Series nMOS don't stack thresholds for a DC-passed 1; they stack resistance, not voltage loss.
The real cost. What series does worsen: speed. The devices' channel resistances add ( $R_{1} + R_{2} + R_{3}$ ) and node capacitances give an RC delay that grows roughly with the square of chain length. Why this step? PTL has no gain/drive; long chains are slow even when the final voltage is fine.

Conclusion: The student is wrong — the far end sits at $1.4 V$ (one threshold drop), not $0.6 V$ . Series length costs delay, not extra voltage.

Verify: Correct far-end voltage $= 1.8 - 0.4 = 1.4 V$ (one drop), not the student's $0.6 V$ . So $1.4 \neq = 0.6$ → the claim fails. ✓

Example 9 — Zero / degenerate cases (cell J)

Forecast: (a) does the output track the input or hold? (b) how high can the 1 get?

(a) Gate OFF. With the gate at 0, $V_{GS} = V_{G} - V_{S} = 0 - V_{S} \leq 0 < V_{t n}$ : the channel never forms. Why this step? No gate push → no channel → the switch is open.
(a) Result. No connection: the output node is left floating at whatever charge it already had (a high-impedance / "Z" state). It does not follow the input. Why this step? An OFF pass transistor isolates — exactly how a MUX de-selects a path.
(b) Low $V_{D D}$ . Weak 1 $= V_{D D} - V_{t n} = 0.6 - 0.4 = 0.2 V$ . Why this step? The threshold drop is a fixed absolute number; as $V_{D D}$ shrinks it eats a bigger fraction.
(b) Result. $0.2 V$ is nowhere near a usable logic 1 — the passed "1" is basically indistinguishable from a 0. This is why deep-submicron / low-voltage designs abandon bare nMOS pass logic and use transmission gates or restoration. In the extreme where $V_{D D} \to V_{t n}$ , the weak 1 $\to 0$ : an nMOS can pass no usable 1 at all. Why this step? The weak-1 problem goes from annoying to fatal at low $V_{D D}$ .

Verify: (a) gate OFF → $V_{GS} \leq 0 < V_{t n}$ → floating (no defined output, logically Z) ✓. (b) $0.6 - 0.4 = 0.2 V$ ✓, far below any 1-threshold → unusable; and $V_{D D} \to V_{t n}$ gives weak 1 $\to 0$ ✓.

Recall Which cell was your weakest?

If you fumbled Ex 8 (series chain), reread: series nMOS stack resistance, not threshold drops — only one $V_{t n}$ is lost. ::: Series pass transistors cost delay (RC), not extra voltage drop.

Connections

Transmission Gate — the fix used in Ex 4
CMOS Inverter — the leakage victim in Ex 5
Threshold Voltage & Body Effect — Ex 6's extra penalty
Multiplexers — Ex 7's datapath
Static CMOS Logic — the count-heavy alternative
Dynamic Power vs Static Leakage — why the weak 1 costs power