Pass-transistor logic: Exercises — Hardware deep dive

This is the self-test page for Pass-transistor logic. Every problem has a full worked solution hidden behind a collapsible box — try first, then reveal. Problems climb five levels: L1 Recognition → L2 Application → L3 Analysis → L4 Synthesis → L5 Mastery.

Symbols you will use everywhere (defined once, here):

Look at the red curve: it is $V_{o u t}$ climbing over time. It flattens exactly at $V_{D D} - V_{t n}$ , never reaching the dashed rail. That gap is the whole subject.

Level 1 — Recognition

L1.1

In a pass transistor, which terminal receives the data signal, and which is the control?

Recall Solution

Data enters at a source/drain terminal and leaves at the other source/drain. The gate is the control (steering) input. Contrast with Static CMOS Logic, where inputs only drive gates and the output is pulled to a rail.

L1.2

Fill in: nMOS passes a strong ___ and a weak ___. pMOS passes a strong ___ and a weak ___.

Recall Solution

nMOS: strong 0, weak 1. pMOS: strong 1, weak 0. Mnemonic: "N passes low, P passes high."

L1.3

True/False: tying an nMOS gate to $V_{D D}$ makes it pass a full $V_{D D}$ at the output.

Recall Solution

False. It passes only up to $V_{D D} - V_{t n}$ . The gate being high does not help once the source (output) rises — see the derivation in Threshold Voltage & Body Effect.

Level 2 — Application

L2.1

$V_{D D} = 1.8$ V, $V_{t n} = 0.4$ V, ignore body effect. A single nMOS (gate at $V_{D D}$ ) passes an input of $1.8$ V to an empty node. What is the final $V_{o u t}$ ?

Recall Solution

Conduction stops at $V_{GS} = V_{t n}$ , i.e. $V_{D D} - V_{o u t} = V_{t n}$ . $V_{o u t, m a x} = V_{D D} - V_{t n} = 1.8 - 0.4 = 1.4 V .$

L2.2

Same device, but now the input is 0 V and the node starts charged at $1.8$ V. Final $V_{o u t}$ ?

Recall Solution

Now the node discharges; the low side becomes the source, $V_{S} \to 0$ . Then $V_{GS} = V_{D D} - 0 = 1.8 V ≫ V_{t n}$ the whole way, so the device stays strongly ON. $V_{o u t} = 0 V (a perfect 0) .$

L2.3

$V_{D D} = 3.3$ V, $V_{tp} = - 0.5$ V. A single pMOS (gate at GND) passes $0$ V toward a node charged high. What is the lowest voltage it can deliver (its weak '0')?

Recall Solution

A pMOS conducts while $V_{S G} = V_{S} - V_{G} > ∣ V_{tp} ∣$ . Here $V_{G} = 0$ , and the falling output is the source $V_{S} = V_{o u t}$ . Conduction stops at $V_{o u t} - 0 = ∣ V_{tp} ∣$ : $V_{o u t, m i n} = ∣ V_{tp} ∣ = 0.5 V .$ Symmetric to the nMOS story: pMOS = strong 1, weak 0.

Level 3 — Analysis

L3.1

Take L2.1's weak '1' of $1.4$ V and feed it to a CMOS inverter whose pMOS has $V_{tp} = - 0.4$ V ( $V_{D D} = 1.8$ V). Is that inverter's pMOS fully off? Explain with numbers.

Recall Solution

The inverter pMOS turns off only when $V_{S G} = V_{D D} - V_{in} \leq ∣ V_{tp} ∣$ , i.e. $V_{in} \geq V_{D D} - ∣ V_{tp} ∣ = 1.8 - 0.4 = 1.4$ V. The input is exactly $1.4$ V → $V_{S G} = 0.4 = ∣ V_{tp} ∣$ → the pMOS sits right at threshold, barely off. Any body-effect worsening pushes the input below $1.4$ V and the pMOS conducts → static leakage. This is exactly why CMOS Inverter loads reveal the weak-'1' problem; see Dynamic Power vs Static Leakage.

L3.2

Now include the body effect. Given $V_{t n 0} = 0.4$ V, $γ = 0.4 V$ , $2 ϕ_{F} = 0.7$ V, $V_{D D} = 1.8$ V. The passed '1' degrades until $V_{D D} - V_{o u t} = V_{t n} (V_{o u t})$ with $V_{t n} = V_{t n 0} + γ (2 ϕ_{F} + V_{o u t} - 2 ϕ_{F}) .$ Solve for the actual weak '1'. (One fixed-point iteration is enough to see the trend.)

Recall Solution

We need $V_{o u t} = V_{D D} - V_{t n} (V_{o u t})$ . Start with the no-body value $V_{o u t}^{(0)} = 1.4$ V. $V_{t n} (1.4) = 0.4 + 0.4 (0.7 + 1.4 - 0.7) = 0.4 + 0.4 (1.4491 - 0.8367) = 0.4 + 0.2450 = 0.6450.$ $V_{o u t}^{(1)} = 1.8 - 0.6450 = 1.155 V .$ Iterate once more: $V_{t n} (1.155) = 0.4 + 0.4 (1.855 - 0.8367) = 0.4 + 0.4 (1.3620 - 0.8367) = 0.6101,$ $V_{o u t}^{(2)} = 1.8 - 0.6101 = 1.190 V .$ Converges near $\approx 1.18 V$ — noticeably worse than the $1.4$ V no-body estimate. Body effect makes the weak '1' weaker still.

The red dot is where the two curves cross — that intersection is the final degraded '1'. The body-effect curve (rising $V_{t n}$ ) pushes the crossing lower.

Level 4 — Synthesis

L4.1

Design a 2:1 MUX $Y = S \cdot A + \overset{ˉ}{S} \cdot B$ in PTL. State transistor count (excluding the inverter for $\overset{ˉ}{S}$ ) and describe operation.

Recall Solution

One nMOS: gate $= S$ , passes $A$ to $Y$ .
One nMOS: gate $= \overset{ˉ}{S}$ , passes $B$ to $Y$ .
Drains tied together at $Y$ . Count: 2 transistors (+ 1 inverter to make $\overset{ˉ}{S}$ ). Exactly one select line is high, so exactly one pass transistor is ON → the chosen input is steered to $Y$ . This is the killer app in Multiplexers.

L4.2

Your L4.1 MUX passes a weak '1' when the selected input is high. Redesign so the output is rail-to-rail clean. Two acceptable answers — give both.

Recall Solution

Answer A — Transmission gates. Replace each nMOS with a Transmission Gate (nMOS ∥ pMOS, complementary gates). The nMOS carries the low half, the pMOS the high half → full swing both ways. Cost: 4 transistors + complemented controls. Answer B — Restoring pMOS. Feed the degraded $Y$ into an inverter and add a feedback pMOS from $V_{D D}$ to $Y$ , gated by the inverter output. When the inverter output goes low, this pMOS pulls the weak-'1' node all the way to $V_{D D}$ , killing the leakage.

L4.3

Build XOR $Y = A \oplus B$ using PTL by passing variables, not rails. Write the steering equation and the transistor list.

Recall Solution

$Y = \overset{ˉ}{B} \cdot A + B \cdot \overset{ˉ}{A} .$

nMOS: gate $= \overset{ˉ}{B}$ , passes $A$ .
nMOS: gate $= B$ , passes $\overset{ˉ}{A}$ .
drains → $Y$ . XOR becomes a tiny MUX that routes $A$ or $\overset{ˉ}{A}$ depending on $B$ . Impossible to think of this way in pure pull-up/pull-down Static CMOS Logic, where inputs only touch gates.

Level 5 — Mastery

L5.1

You chain three nMOS pass transistors in series (each gate at $V_{D D}$ ), passing a '1' through all three to an output node. Ignoring body effect, what is the final $V_{o u t}$ ? Does each stage subtract another $V_{t n}$ ?

Recall Solution

No — the drop is not cumulative. Only the transistor whose source is the final rising output node loses the threshold. Intermediate nodes settle, and the last stage's source is the output at $V_{o u t}$ . The steady-state high is set by the last device that must hold the node against its own $V_{GS} = V_{t n}$ cutoff: $V_{o u t, m a x} = V_{D D} - V_{t n} = 1.8 - 0.4 = 1.4 V .$ What does worsen with the chain is speed (series RC of stacked channels), not the DC high level. Common exam misconception: people expect $1.8 - 3 \times 0.4 = 0.6$ V — wrong.

L5.2

A designer swaps the nMOS pass transistors in a MUX for pMOS pass transistors to "fix the weak 1." $V_{D D} = 1.8$ V, $∣ V_{tp} ∣ = 0.4$ V. What now happens to a passed '0', and why is this not a free win?

Recall Solution

pMOS passes a strong 1 but a weak 0: the '0' only falls to $∣ V_{tp} ∣ = 0.4 V$ , never reaching GND. So you traded a weak '1' for a weak '0' — the following inverter's nMOS may not fully turn off ( $0.4$ V vs $V_{t n} = 0.4$ V → right at threshold, leaks). No free win; the only true fix for both rails is the Transmission Gate (nMOS ∥ pMOS) or a restorer.

L5.3

General principle: for a pass transistor, which rail does it degrade, and state the one-line rule that predicts it from the device type without any algebra.

Recall Solution

Rule: a pass transistor is strong toward the rail its gate can over-drive, and weak toward the rail it approaches.

nMOS gate at $V_{D D}$ : strong toward GND (source stays low, $V_{GS}$ huge), weak toward $V_{D D}$ .
pMOS gate at GND: strong toward $V_{D D}$ (source stays high, $V_{S G}$ huge), weak toward GND. One line: nMOS degrades the high rail, pMOS degrades the low rail.

Connections

CMOS Inverter — the load that exposes weak-'1' leakage (L3)
Transmission Gate — the true both-rail fix (L4, L5)
Static CMOS Logic — the contrast: steering vs pull-up/pull-down
Threshold Voltage & Body Effect — source of the drop (L3.2)
Multiplexers — the MUX built in L4
Dynamic Power vs Static Leakage — why degraded levels cost power