Pass-transistor logic

3.2.10 · Hardware › CMOS Circuit Design

Chapter: CMOS Circuit Design · Subtopic 3.2.10

WHAT hai ek pass transistor?

Static CMOS gate output: node ko ek rail ki taraf transistor ke through pull kiya jaata hai.
PTL: node ko actual input voltage conducting channel ke through copy karke milti hai.

WHY nMOS ek weak '1' pass karta hai (central fact)

Ek nMOS transistor tabhi conduct karta hai (ON rehta hai) jab

$V_{GS} = V_{G} - V_{S} > V_{t n}$

HOW yeh humein takleef deta hai jab '1' pass karna ho:

Maano gate $V_{D D}$ se tied hai aur hum source par $V_{D D}$ input apply kar rahe hain, ek output node (initially 0) ko '1' ki taraf charge karne ki koshish kar rahe hain. Output node voltage ko $V_{o u t}$ kahte hain; yeh nMOS ka source ki tarah kaam karta hai (current iske andar se load mein jaati hai).

WHY nMOS ek perfect '0' pass karta hai: 0 ki taraf discharge hote waqt, source low node hai, $V_{S} \to 0$ , isliye $V_{GS} = V_{D D} - 0 = V_{D D} ≫ V_{t n}$ — device 0 V tak strongly ON rehta hai. Toh:

nMOS: strong 0, weak 1
pMOS (symmetric argument): strong 1, weak 0 (yeh tab ruk jaata hai jab $V_{o u t}$ $∣ V_{tp} ∣$ tak gir jaata hai).

HOW hum weak '1' ko fix karte hain

1. Transmission gate (CMOS pass gate). Ek nMOS ko ek pMOS ke saath parallel mein lagao, complementary gate signals se driven.

2. Level-restoring (swing-restoring) pMOS. nMOS pass transistors ki ek chain ke baad jo ek inverter feed karti hai, ek feedback pMOS $V_{D D}$ se degraded node tak add karo. Jab inverter output low jaata hai, pMOS weak-'1' node ko poori tarah $V_{D D}$ tak pull karta hai, level restore karta hai.

Worked Example 1 — PTL mein 2:1 MUX

Function: $Y = S \cdot A + \overset{ˉ}{S} \cdot B$ .

Build: ek nMOS gate $S$ ke saath $A$ pass karta hai; ek nMOS gate $\overset{ˉ}{S}$ ke saath $B$ pass karta hai; drains $Y$ se tied hain.

Yeh step kyun? Exactly ek select line high hoti hai, isliye exactly ek pass transistor ON hota hai, chosen input ko $Y$ tak steer karta hai. Sirf 2 transistors (+ $\overset{ˉ}{S}$ ke liye inverter) vs. full CMOS ke liye bahut saare.

Check $S = 1, A = 1$ : $A$ -path nMOS ON hai, gate $V_{D D}$ par, ek '1' pass kar raha hai → output $V_{D D} - V_{t n}$ tak degrade hoti hai.

Kyun care karein? Agar $Y$ kisi agle gate ko drive kare, toh woh weak '1' agli pMOS ko fully turn off nahi kar sakti → static leakage. Transmission gate ya restoring inverter se fix karo.

Worked Example 2 — XOR steering

$Y = A \oplus B$ . $A$ aur $\overset{ˉ}{A}$ ko pass signals ki tarah use karo, $B, \overset{ˉ}{B}$ ke saath steered: $Y = \overset{ˉ}{B} \cdot A + B \cdot \overset{ˉ}{A} .$

Yeh step kyun? PTL hume variables khud pass karne deta hai (sirf rails nahi), isliye $A$ aur $\overset{ˉ}{A}$ routed hone wala data ban jaate hain — pure pull-up/pull-down CMOS soch mein yeh mumkin nahi. XOR ek chhota sa MUX ban jaata hai.

Worked Example 3 — voltage numbers

Maano $V_{D D} = 1.8$ V, $V_{t n 0} = 0.4$ V, body effect ignore karo.

Single nMOS se weak '1' out $= 1.8 - 0.4 = 1.4$ V. Kyun: $V_{GS} = V_{t n}$ par conduction ruk jaati hai.
Agli CMOS inverter ko $V_{tp} = - 0.4$ V ke saath feed karo: uski pMOS ko $V_{S G} > 0.4$ chahiye, yaani gate $1.8 - 0.4 = 1.4$ V se neeche. Input exactly $1.4$ V hai → pMOS threshold par bilkul sahi hai, muskil se off hai, leakage hai. Fix kyun matter karta hai: static power ∝ is leakage ke.

80/20 — woh 20% jo tumhare paas hona chahiye

nMOS = strong 0, weak 1 ( $V_{D D} - V_{t n}$ ); pMOS = strong 1, weak 0.
Reason: conduction ko $V_{GS} > V_{t n}$ chahiye, aur passed node hi source hai.
Weak levels ko transmission gate ya restoring pMOS se fix karo.
PTL transistor count ko level degradation + no drive ke badle mein trade karta hai.

Recall Feynman: ek 12-saal ke bacche ko explain karo

Ek paani ki pipe socho jisme ek valve hai jo tum ek spring se kholte ho. Spring ki pull depend karti hai ki doosri taraf ka paani kitna oopar hai. Paani baahir jaane dene ke liye (doosri taraf khaali karne ke liye), spring mazboot rehti hai — aasaan. Lekin doosri taraf bharne ke liye, jaise paani upar uthta hai woh spring ko peeche dhakel deta hai, aur ek point par valve poora bharne se pehle band ho jaata hai. Toh yeh valve khaali karne mein great hai lekin bharte waqt tank ko thoda sa kam chhod deta hai. Woh "thoda kam chhod deta hai" hi reason hai ki nMOS switch weak '1' deta hai. Poora bharne ke liye, tum ek doosra, ulta valve (pMOS) add karte ho — saath milke yeh dono kaam karte hain.

Flashcards

Why can't a single nMOS pass a strong logic '1'?

Jaise output badhta hai,

V_{GS} = V_{D D} - V_{o u t}

girta hai; conduction tab ruk jaati hai jab

V_{GS} = V_{t n}

, isliye

V_{o u t, m a x} = V_{D D} - V_{t n}

Maximum voltage an nMOS pass transistor delivers (gate at

V_{D D}

V_{D D} - V_{t n}

(body effect ke saath aur bhi neeche).

nMOS pass transistor strengths?

Strong '0', weak '1'.

pMOS pass transistor strengths?

Strong '1', weak '0'.

What is a transmission gate?

nMOS ∥ pMOS with complementary gates, passing both rails full-swing.

Two ways to restore a degraded '1' from an nMOS pass chain?

Transmission gate; ya ek feedback (level-restoring) pMOS to

V_{D D}

Transistor count of a PTL 2:1 MUX (excluding inverter)?

2 (ek nMOS per data input,

S

aur

\overset{ˉ}{S}

se steered).

Downside of feeding a degraded '1' into a CMOS inverter?

Inverter ki pMOS fully turn off nahi ho sakti → static leakage / power.

How does body effect worsen the weak '1'?

V_{S B} = V_{o u t}

bada hota hai,

V_{t n}

aur badhata hai, isliye '1'

V_{D D} - V_{t n 0}

se bhi neeche hoti hai.

Why does an nMOS pass a perfect '0'?

Discharge karte waqt,

V_{S} \to 0

isliye

V_{GS} = V_{D D} ≫ V_{t n}

: 0 V tak strongly ON rehta hai.

Connections

CMOS Inverter — woh load jo weak-'1' leakage reveal karta hai
Transmission Gate — standard PTL fix
Static CMOS Logic — contrast: pull-up/pull-down vs signal steering
Threshold Voltage & Body Effect — threshold drop ka source
Multiplexers — PTL ka killer app
Dynamic Power vs Static Leakage — degraded levels ki cost

The Big Picture