Worked examples — Multiplexers (2 - 1, 4 - 1, n - 1)

Before anything: three plain words you will keep needing.

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The scenario matrix

Every MUX question falls into one of these cells. The worked examples below are each tagged with the cell they cover.

Cell	Case class	What makes it tricky
A	Direct selection — read $Y$ given selects + inputs	convert address correctly, MSB order
B	Degenerate select = all-zeros	picks $I_0$, easy to skip
C	Degenerate select = all-ones	picks the last input $I_{2^n-1}$
D	Function on a full $2^n:1$ MUX	wire inputs = truth-table column
E	Function on a smaller MUX (Shannon)	inputs become $0,1,v,\bar{v}$
F	Cascading — build big MUX from small ones	which bit selects the group
G	Enable line active/inactive	$E=0$ forces $Y=0$ (or high-Z)
H	Sizing / limiting — how many selects, how many chips	$\lceil {\log }_{2}N\rceil$, ceiling for non-powers of 2
I	Real-world word problem	translate English into address bits
J	Exam twist — inputs are variables, not constants	don't confuse input value with select value

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Example 1 — Cell A: plain selection

1. Convert the address. $S_1{S}_0=10\Rightarrow 1\times 2+0\times 1=2$. Why this step? The select bits are a base-2 number; that number is the input index. High bit $S_1$ first.
2. Pick the input. Address $2\Rightarrow Y=I_2$. Why? By definition $Y=I_k$ with $k=$ the address.
3. Read its value. $I_2=1$, so $Y=1$.

Verify: Exactly one minterm is 1 for any select value (they are mutually exclusive), so no other input can leak. $Y=1$.

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Example 2 — Cell B: all-zero select (degenerate low)

1. Address = 0. $000_2=0$. Why? Even the all-zero select is a valid address; it names input $I_0$.
2. $Y=I_0=0$. Why this step? People assume "zero select = MUX off." Not true — a plain MUX has no off state; it always passes exactly one input. $I_0$ is that input here.

Verify: minterm $m_0={\bar{S}}_2{\bar{S}}_1{\bar{S}}_0=1$ only when all selects are 0. So $Y=m_0{I}_0=I_0=0$. ✅

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Example 3 — Cell C: all-one select (degenerate high)

1. Address $=11_2=3$. Why? $1\times 2+1\times 1=3$ — the largest index a 2-bit address can name.
2. $Y=I_3=1$. Why this step? All-ones select always picks the last input $I_{2^n-1}$, never $I_1$. This is the mirror of Cell B.

Verify: $m_3=S_1{S}_0=1$ here, others $0$; $Y=I_3=1$. General rule: all-ones on $n$ selects $\Rightarrow$ index $2^n-1$. ✅

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Example 4 — Cell D: any function on a full 4:1 MUX

1. Build the truth table. Compute $F$ for each row.

   $A$	$B$	$\bar{B}$	$F=A+\bar{B}$	row $k=(AB{)}_2$
   0	0	1	1	0
   0	1	0	0	1
   1	0	1	1	2
   1	1	0	1	3

   Why this step? A full $2^n:1$ MUX is a truth-table copier: row $k$ of the table = the value you hard-wire onto $I_k$.

2. Wire inputs = the $F$ column. $I_0=1,I_1=0,I_2=1,I_3=1$ (all constants 0/1). Why? When the actual $A,B$ appear on the selects, the MUX routes exactly that row's constant to $Y$.

Verify: Try $A=0,B=1$: selects $=01=1\Rightarrow Y=I_1=0$, and $F(0,1)=0+\bar{1}=0+0=0$. ✅ Try $A=1,B=1$: selects $=11=3\Rightarrow Y=I_3=1$, $F=1+0=1$. ✅ See Boolean Algebra Minterms for why the SOP form guarantees this.

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Example 5 — Cell E: same function, smaller MUX (Shannon on B)

This is Shannon Expansion: split $F$ into the case $B=0$ and the case $B=1$, and let the leftover variable $A$ live in the data inputs.

1. Write the 2:1 equation with $B$ as select. $Y=\bar{B}{I}_0+B{I}_1.$ Why this step? Whatever we put on $I_0$ is what $Y$ equals when $B=0$; $I_1$ is what $Y$ equals when $B=1$.
2. Case $B=0$. $F=A+\bar{0}=A+1=1$. So $I_0=1$. Why? Fix $B=0$ and simplify $F$ — the result is a function of the leftover variable $A$ (here it collapses to the constant 1).
3. Case $B=1$. $F=A+\bar{1}=A+0=A$. So $I_1=A$. Why? Same, with $B=1$. Now the leftover $A$ survives as a live wire — an input can be a variable, not just 0/1.

Verify: $A=1,B=0$: $Y=\bar{B}{I}_0=1\cdot 1=1$; $F=1+1=1$. ✅ $A=0,B=1$: $Y=B{I}_1=1\cdot A=0$; $F=0+0=0$. ✅ $A=1,B=1$: $Y=I_1=A=1$; $F=1+0=1$. ✅ Matches the full table in Example 4.

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Example 6 — Cell F: cascading (build an 8:1 from 4:1 + 2:1)

1. Split by the top bit. Low group $I_0..I_3$, high group $I_4..I_7$. Why this step? $S_2$ is worth $4$. Indices $0\text{–}3$ all have $S_2=0$; indices $4\text{–}7$ all have $S_2=1$. So $S_2$ separates the two halves.
2. Feed $S_1{S}_0$ to both 4:1 MUXes. MUX-L outputs $I_{(S_1{S}_0)}$ from the low group; MUX-H outputs $I_{4+(S_1{S}_0)}$. Why? $S_1{S}_0$ chooses the position within a group of four (the low 2 bits of the address).
3. The 2:1 MUX (select $S_2$) picks a group. $Y={\bar{S}}_2(\text{MUX-L})+S_2(\text{MUX-H})$.

Trace $S_2{S}_1{S}_0=101$: $S_1{S}_0=01=1$, so MUX-L emits $I_1$ and MUX-H emits $I_{4+1}=I_5$. $S_2=1$, so the 2:1 forwards MUX-H $\Rightarrow Y=I_5$.

Verify: $101_2=5$, and we got $Y=I_5$. The group bit and the within-group bits reassembled the full address. ✅

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Example 7 — Cell G: the enable line

1. Compute the inner MUX value. Address $01=1\Rightarrow$ inner $=I_1=1$. Why? The bracket is just the ordinary 4:1 expression from Example 1.
2. (a) $E=1$: $Y=1\cdot 1=1$. Why? Enable-high passes the MUX result unchanged.
3. (b) $E=0$: $Y=0\cdot 1=0$. Why this step? $E$ multiplies everything; a single 0 factor kills the product. On a tri-state part this becomes high-Z (the output floats off the bus) instead of a hard 0.

Verify: $E=1\Rightarrow Y=1$; $E=0\Rightarrow Y=0$ regardless of inputs. This is exactly what lets many MUXes share one bus. ✅

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Example 8 — Cell H: sizing and limiting behaviour

The rule from the parent: for $N$ inputs, selects $=\lceil {\log }_{2}N\rceil$ (the smallest integer $\ge {\log }_{2}N$).

1. (a) 16 inputs. ${\log }_{2}16=4$ exactly $\Rightarrow$ 4 selects. Why the log? $n$ bits address $2^n$ inputs; invert that to get $n={\log }_{2}N$.
2. (b) 12 inputs. ${\log }_{2}12=3.58\dots$, not an integer. $\lceil 3.58\rceil =4\Rightarrow$ 4 selects. Why the ceiling? 3 bits only address $2^3=8$ inputs — too few for 12. You must round up; 4 addresses cover $16\ge 12$ (the extra 4 addresses go unused).
3. (c) 16:1 from 4:1s. Four 4:1 MUXes fan into one 4:1 selector $\Rightarrow$ 5 MUXes. Why? Bottom 2 select bits drive the four data MUXes (each covers 4 inputs); top 2 bits drive the selector that picks among the four groups. $4\times 4=16$ inputs, $2+2=4$ select bits.

Verify: $\lceil {\log }_{2}16\rceil =4$, $\lceil {\log }_{2}12\rceil =4$, chip count $=4+1=5$. ✅

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Example 9 — Cell I: real-world word problem

1. Identify the parts. 4 sensors = data inputs; 2 switches = select lines; 1 shared bus = output $Y$. This is literally a 4:1 MUX. Why this step? "Many sources, one shared wire, a control that picks one" is the exact signature of a MUX — the same reason a MUX exists (a shared bus can't carry all four at once).
2. Convert the switches. $T_1{T}_0=10=2$. Why? $T_1$ is the MSB, worth 2.
3. Read the wiring map. Address 2 $\to I_2\to$ temperature.

Verify: $10_2=2$, mapped to $I_2=$ temp. If the switches read $11$ we'd get $I_3=$ RPM instead — sanity-checks against the mapping. ✅

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Example 10 — Cell J: exam twist (variable input)

1. Substitute carefully. $Y=\bar{S}{I}_0+S{I}_1=\bar{A}\cdot A+A\cdot \bar{A}$. Why this step? Replace each symbol with its wired value — $S$, $I_0$, $I_1$ are all $A$-expressions here.
2. Simplify with $x\bar{x}=0$. $\bar{A}\cdot A=0$ and $A\cdot \bar{A}=0$, so $Y=0+0=0$. Why? A variable ANDed with its own complement is always 0 — they can't both be 1.
3. Conclusion: $Y=0$, the constant zero function.

Verify: $A=0$: $Y=\bar{0}\cdot 0+0\cdot \bar{0}=0$. $A=1$: $Y=\bar{1}\cdot 1+1\cdot \bar{1}=0$. Constant 0 confirmed. ✅ (Moral: an input being a variable is fine — but always substitute, never eyeball.)

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Recall Case coverage self-test

• All-zero select on an 8:1 picks? ::: $I_0$.
• All-one select on an 8:1 picks? ::: $I_7$ (the last input).
• Selects for a 12:1 MUX? ::: $\lceil {\log }_{2}12\rceil =4$.
• On a full 4:1 MUX, what do you wire the inputs to? ::: the truth-table output column of the function.
• Shannon on a 2:1 MUX: what can each input be? ::: one of $0,1,v,\bar{v}$.
• Which bit selects the group when cascading to an 8:1? ::: the MSB $S_2$.
• $E=0$ on an active-high MUX gives? ::: $Y=0$ (or high-Z on tri-state).

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Connections

• Multiplexers (2 - 1, 4 - 1, n - 1) — the parent: definitions and derivations these examples exercise.
• Boolean Algebra Minterms — why the SOP wiring in Example 4 is exact.
• Shannon Expansion — the shrink trick in Example 5.
• Decoders — the minterm generator inside the MUX.
• Demultiplexers — the inverse, for contrast in word problems.
• Tri-state Buffers — what $E=0$ really does on a shared bus (Example 7).
• Combinational Logic Design — MUX as a universal building block.