Multiplexers (2 - 1, 4 - 1, n - 1): Question bank — Hardware deep dive

Before we start, one shared vocabulary reminder so no symbol appears un-earned:

See the parent Multiplexers topic note for the full derivations these traps are built on.

True or false — justify

A 4:1 MUX has 4 select lines.

False. A 4:1 MUX has 4 inputs but only

⌈ lo g_{2} 4 ⌉ = 2

select lines; the selects address inputs, so it is a log relationship, not one-per-input.

An n:1 MUX always needs n select lines.

False. For

N

inputs you need

⌈ lo g_{2} N ⌉

selects. The letter "n" in "n:1" refers to inputs (or the address width, depending on the book) — never assume it is the select count. See Combinational Logic Design.

For any given value on the select lines, exactly one minterm equals 1.

True. The minterms of the select variables are mutually exclusive and exhaustive: each select combination makes precisely one product-term true, so exactly one

I_{k}

reaches the output and the rest are multiplied by 0.

A multiplexer and a demultiplexer are the same device used backwards.

Partly false. They are inverse operations (many→one vs one→many) but different circuits: a MUX has one output, a DEMUX has many. You cannot literally reverse the signal flow through the same gates. See Demultiplexers.

2^{n} : 1

MUX can implement any Boolean function of

n

variables.

True. Put the

n

variables on the selects and wire each

I_{k}

to the truth-table output of row

k

(a constant 0 or 1). The MUX then copies the correct row for every input — it is a hardware lookup table. See Boolean Algebra Minterms.

With

S_{1} S_{0} = 10

, the MUX selects input

I_{1}

False.

S_{1}

is the most-significant bit, so

1 0_{2} = 2

, selecting

I_{2}

. Always convert the select bits to a number, high bit first.

If two data inputs happen to carry the same value, the output could be ambiguous.

False. The output is never ambiguous — the select value uniquely picks one input regardless of what the others carry. Equal inputs are irrelevant; only the addressed one is copied.

A MUX contains a decoder inside it.

True. The minterm generator at the heart of a MUX is a decoder: a decoder produces all

2^{n}

minterms of the selects, and the MUX ANDs each with its input and ORs the results. So MUX = decoder + AND–OR.

Setting the enable line

E = 0

on an active-high MUX makes the output equal to

I_{0}

False.

E = 0

forces

Y = 0

(or high-Z on tri-state parts) regardless of selects.

E

gates the whole MUX expression:

Y = E \cdot (MUX expr)

Shannon expansion lets a

2^{n - 1} : 1

MUX implement an

n

-variable function.

True. Put

n - 1

variables on the selects; each data input then becomes one of

{0, 1, v, \overset{v}{ˉ}}

where

v

is the leftover variable. Half the address space is folded into the input wires. See Shannon Expansion.

Spot the error

"The 2:1 MUX equation is

Y = S I_{0} + \overset{ˉ}{S} I_{1}

Swapped. It should be

Y = \overset{ˉ}{S} I_{0} + S I_{1}

: input

I_{0}

is chosen when

S = 0

(i.e.

\overset{ˉ}{S} = 1

), so

I_{0}

must pair with

\overset{ˉ}{S}

, not

S

"To build a 16:1 MUX I need 16 select lines."

Wrong count.

⌈ lo g_{2} 16 ⌉ = 4

select lines. 16 inputs are addressed by 4 bits, since

2^{4} = 16

"A MUX with

n

inputs is universal for

n

-variable functions."

Off by an exponent. A MUX with

2^{n}

inputs is universal for

n

variables (the

n

variables ride the selects). An

n

-input MUX has only

lo g_{2} n

selects, so it is universal for

lo g_{2} n

variables.

"To XOR

A, B

on a 4:1 MUX I wire

I_{0} = 1, I_{1} = 0, I_{2} = 0, I_{3} = 1

Inverted. XOR's truth table is

F (00) = 0, F (01) = 1, F (10) = 1, F (11) = 0

, so the correct wiring is

I_{0} = 0, I_{1} = 1, I_{2} = 1, I_{3} = 0

. The student wired XNOR by mistake.

Y = \overset{ˉ}{S}_{1} \overset{ˉ}{S}_{0} I_{0} + \overset{ˉ}{S}_{1} S_{0} I_{1} + S_{1} S_{0} I_{2} + S_{1} \overset{ˉ}{S}_{0} I_{3}

is a valid 4:1 MUX."

Mismatched terms.

I_{2}

must pair with

S_{1} \overset{ˉ}{S}_{0}

(

= 2

) and

I_{3}

with

S_{1} S_{0}

(

= 3

); here they are swapped, so it selects the wrong inputs for

S_{1} S_{0} = 10

and

11

"Enable doesn't change the logic — you can always ignore it."

Dangerous. Without accounting for

E

, cascaded MUXes on a shared bus would all drive the line at once and fight.

E

is what makes bus sharing and cascading safe.

"An 8:1 MUX built from two 4:1s needs the top bit

S_{2}

on both 4:1 MUXes."

Wrong wiring. The two 4:1 MUXes both take

S_{1} S_{0}

; the top bit

S_{2}

drives the final 2:1 MUX that chooses between the two groups.

S_{2}

picks the group,

S_{1} S_{0}

picks within it.

Why questions

Why is the number of select lines a logarithm of the input count, not the count itself?

Because

n

select bits form a binary number that ranges over

2^{n}

distinct values, and each value is a distinct address. To cover

N

inputs you solve

2^{n} \geq N

, giving

n = ⌈ lo g_{2} N ⌉

Why can exactly one — and only one — input ever reach the output?

Because the select minterms are mutually exclusive: for any select value, one minterm is 1 and all others are 0. Multiplying each input by its minterm zeroes out every input except the addressed one.

Why does a MUX act like a truth-table copier?

When the function's variables sit on the selects, the select value is the truth-table row index. Wiring each

I_{k}

to that row's output value means the MUX literally reads out the table entry for the current input.

Why do we ever bother building a function with a smaller MUX via Shannon expansion?

Fewer select lines and inputs means fewer address wires and a cheaper chip. By putting the leftover variable (as

v

\overset{v}{ˉ}

) onto data lines instead of a select, we trade one select for a bit of extra input logic.

Why is the general MUX equation written as a sum (OR) of products?

Each product (minterm · input) handles exactly one select case; ORing them combines all cases into one expression. Because only one product is ever nonzero, the OR just passes that single surviving term — clean selection.

Why is

S_{1}

, not

S_{0}

, treated as the most-significant bit?

By convention the higher subscript is the higher place value, so

S_{1}

carries weight 2 and

S_{0}

carries weight 1. This makes

S_{1} S_{0} = 1 0_{2} = 2

address

I_{2}

, keeping the index equal to the binary number.

Why must the enable line multiply the whole expression rather than individual inputs?

Because enable must force the single output to a known state (0 or high-Z) no matter which input is addressed. Gating the whole SOP with

E

guarantees

Y = 0

when

E = 0

for every select combination at once.

Edge cases

What does a "1:1 MUX" mean, and how many selects does it have?

It has one input and

⌈ lo g_{2} 1 ⌉ = 0

select lines — a plain wire (or a buffer). With nothing to choose between, there is nothing to select.

What happens if all data inputs of a MUX are tied to 0?

The output is always 0 regardless of the selects, because every surviving term is

minterm \cdot 0 = 0

. This is a legitimate (if useless) constant-0 generator.

What is the output when the enable is off but a valid address sits on the selects?

On an active-high MUX,

Y = 0

(or high-Z on tri-state parts). The address is computed internally but the enable gate blocks it from reaching the output.

For a 2:1 MUX, what function of the selects is the output when

I_{0} = 0

and

I_{1} = 1

Y = \overset{ˉ}{S} \cdot 0 + S \cdot 1 = S

. The MUX becomes a buffer that simply passes the select line through — a handy identity for function-building.

For a 2:1 MUX with

I_{0} = 1, I_{1} = 0

, what does the output compute?

Y = \overset{ˉ}{S} \cdot 1 + S \cdot 0 = \overset{ˉ}{S}

. The MUX becomes an inverter of the select line — showing a single 2:1 MUX can realise NOT.

What if

N

is not a power of 2 — say a 6:1 MUX?

You still need

⌈ lo g_{2} 6 ⌉ = 3

select lines (since

2^{2} = 4 < 6 \leq 8 = 2^{3}

). Two of the eight addresses go unused, so those two select combinations select nothing meaningful (often forced to 0).

Connections

Decoders — the minterm generator these traps keep pointing back to.
Demultiplexers — the inverse device the MUX is constantly confused with.
Boolean Algebra Minterms — why exactly one term survives.
Shannon Expansion — the shrink-the-MUX trick.
Tri-state Buffers — the enable / high-Z edge cases.
Combinational Logic Design — MUX as universal block.