3.3.5 · Hardware › Combinational Circuits
Ek multiplexer ek digital switch hai: iske paas bahut saare data inputs hote hain, kuch select lines hoti hain, aur ek output hota hai. Select lines ek rotary knob ki position ki tarah kaam karti hain — ye decide karti hain ki kaun sa input output pe copy hoga. "Multiplex" = "bahut saari cheezein ek line mein."
Intuition Ye exist kyun karta hai
Wires mehnge hote hain. Agar 4 alag data sources ko EK bus/output share karni ho, toh hum unhe directly connect nahi kar sakte (woh aapas mein fight karenge). MUX hamare liye electronically ek source ko ek baar mein choose karne ka kaam karta hai. Ye routing ke liye ek universal building block bhi hai, aur — surprisingly — ye koi bhi Boolean function implement kar sakta hai (WHAT jo ise deep banata hai: ek 2 n : 1 MUX, n -variable function ke liye ek lookup table hai).
Definition n:1 Multiplexer
Ek aisa device jiske paas 2 n data inputs I 0 … I 2 n − 1 , n select lines S n − 1 … S 0 , aur ek output Y hota hai. Output us data input ke barabar hota hai jiska index select lines pe binary number ke barabar ho:
Y = I k where k = ( S n − 1 … S 1 S 0 ) 2
N inputs ke liye kitni select lines chahiye: kyunki n bits 2 n inputs ko address karti hain,
n = ⌈ log 2 N ⌉ .
Hum equation us tarah banate hain jaise ek decoder karta hai: har input ko select variables ke us minterm ke saath AND kiya jaata hai jo uski taraf "point" karta hai, aur ye saare products OR kar diye jaate hain.
Hum chahte hain Y = I 0 jab S = 0 aur Y = I 1 jab S = 1 . "S = 0 hone par" ko term S ˉ capture karta hai; "S = 1 hone par" ko S capture karta hai. Toh:
Y = S ˉ I 0 + S I 1
Do selects S 1 S 0 chaar minterms dete hain. Input I k tab pass hota hai jab S 1 S 0 ki value k ho:
S 1
S 0
minterm
passes
0
0
S ˉ 1 S ˉ 0
I 0
0
1
S ˉ 1 S 0
I 1
1
0
S 1 S ˉ 0
I 2
1
1
S 1 S 0
I 3
Y = k = 0 ∑ 2 n − 1 m k I k
jahaan m k select variables ka wo minterm hai jo k se correspond karta hai. Ye sum-of-products literally ek decoder (minterms) hai jo AND–OR logic ko feed kar raha hai.
Intuition High-value insight
Ek 2 n : 1 MUX jisme n variables select lines pe hain, woh ek truth-table copier hai. Har data input I k ko row k ki truth-table output value se (0 ya 1 constant) wire kar do. Tab Y = tumhara function. Isliye ek chip koi bhi n -input function implement kar sakti hai.
Trick (Shannon expansion): ek n -variable function ko chhote 2 n − 1 : 1 MUX se banane ke liye, n − 1 variables ko selects pe rakho; har data input baaki bache variable v ke { 0 , 1 , v , v ˉ } mein se ek ban jaata hai.
F ( A , B ) = A ⊕ B ko 4:1 MUX se implement karo
Selects S 1 S 0 = A B . XOR truth table: F ( 0 , 0 ) = 0 , F ( 0 , 1 ) = 1 , F ( 1 , 0 ) = 1 , F ( 1 , 1 ) = 0 .
Toh wire karo I 0 = 0 , I 1 = 1 , I 2 = 1 , I 3 = 0 .
Ye step kyun? Har I k simply function ka us row ka output hai — MUX automatically sahi row select kar leta hai.
Worked example Do 4:1 MUXes + ek 2:1 se 8:1 MUX banao (cascading)
8 inputs ko low group I 0 .. I 3 aur high group I 4 .. I 7 mein split karo. Har group ko ek 4:1 MUX mein dalo jo S 1 S 0 se drive ho. Dono MUX outputs ek 2:1 MUX mein jaate hain jo top bit S 2 se drive hoti hai.
Kyun? S 2 group choose karta hai; S 1 S 0 group ke andar choose karta hai — exactly 3-bit address S 2 S 1 S 0 ka matlab.
Real MUX chips mein ek enable E add hoti hai. Typically Y = E ⋅ ( MUX expression ) (active-high), toh E = 0 force karta hai Y = 0 (ya tri-state parts pe high-Z). Enable se tum cascade kar sakte ho aur shared bus pe tri-state kar sakte ho.
Common mistake "n:1 MUX ko n select lines chahiye."
Kyun sahi lagta hai: "n:1" mein n select count jaisa dikhta hai. Reality: N inputs ke liye tumhe ⌈ log 2 N ⌉ selects chahiye. 4:1 mein 2 selects hain, 8:1 mein 3 . Fix: selects inputs ko address karte hain, toh ye ek log relationship hai. (Notation ka dhyan rakho: kuch books "n : 1 " likhte hain jiska matlab n inputs hai; tab selects = log 2 n .)
Common mistake Kaun sa select MSB hai ye swap kar lena.
Kyun sahi lagta hai: dono selects "equal dikhte hain." Reality: S 1 MSB hai, toh S 1 S 0 = 1 0 2 = 2 matlab I 2 select hoga, I 1 nahi. Fix: select bits ko hamesha binary number mein convert karo, high bit pehle.
Common mistake MUX aur DEMUX ko confuse karna.
Kyun sahi lagta hai: dono mein select lines hoti hain. Reality: MUX = many→one; DEMUX = one→many. DEMUX ek input ko bahut saare outputs mein se ek pe route karta hai. Fix: data lines count karo — MUX ka ek output hota hai.
Common mistake Ye bhool jaana ki minterms mutually exclusive hote hain.
Students darte hain ki kai I k output pe leak ho jaayenge. Reality: kisi bhi select value ke liye exactly ek minterm 1 hota hai, baaki sab 0 — clean selection guaranteed hai.
Recall Active recall — answers cover karo
16:1 MUX ke liye selects? → log 2 16 = 4 .
S 2 S 1 S 0 = 101 kaun sa input pick karta hai? → I 5 .
2:1 MUX equation? → Y = S ˉ I 0 + S I 1 .
16:1 banane ke liye kitne 4:1 MUXes? → chaar 4:1 + ek 4:1 selector = 5.
Recall Feynman: ek 12-saal ke bacche ko samjhao
Socho 4 paani ke pipes hain aur ek nal jo ek baar mein sirf ek pipe se pi sakta hai. Tum ek chhota dial ghuma te ho jo 2 clicks mein chalta hai (wo hain 2 select bits = 4 positions). Dial jis number pe hai, usi pipe ka paani bahar aata hai. MUX electricity ke liye wohi magic nal hai — woh sirf ek chosen input ko single output wire pe copy karta hai, baaki sab ko ignore karta hai.
"MUX = Many Under one eXit." Aur selects ke liye: "Log to pick, sum to build" — selects ki sankhya log 2 (inputs) hai, aur equation ek SUM (OR) hai (minterm · input) ka.
Decoders — har MUX ke andar minterm generator (ek MUX = decoder + OR).
Demultiplexers — exact inverse operation (one to many).
Boolean Algebra Minterms — wo SOP form jo humne derive ki.
Shannon Expansion — functions ko chhote MUXes pe shrink kaise karein.
Tri-state Buffers — enable line aur bus sharing.
Combinational Logic Design — MUX as universal function block.
Number of select lines for an N-input MUX? ⌈ log 2 N ⌉ .
Boolean expression of a 2:1 MUX? Y = S ˉ I 0 + S I 1 .
Boolean expression of a 4:1 MUX? Y = S ˉ 1 S ˉ 0 I 0 + S ˉ 1 S 0 I 1 + S 1 S ˉ 0 I 2 + S 1 S 0 I 3 .
Which data input is selected when S 1 S 0 = 10 ? I 2 (since 1 0 2 = 2 ).
General n:1 MUX equation? Y = ∑ k m k I k , minterm of selects times input.
Why can a 2 n : 1 MUX implement any n-variable function? Wire each input to the truth-table value of its row; MUX selects the correct row.
Implement XOR(A,B) on a 4:1 MUX (selects A,B). Inputs? I 0 = 0 , I 1 = 1 , I 2 = 1 , I 3 = 0 .
Implement XOR(A,B) on a 2:1 MUX with A on select. Inputs? I 0 = B , I 1 = B ˉ .
Difference between MUX and DEMUX? MUX = many inputs to one output; DEMUX = one input to many outputs.
Role of the enable line? Gates output; E = 0 forces output 0 / high-Z, enabling cascading and bus sharing.
How to build an 8:1 MUX from smaller ones? Two 4:1 MUXes (select S 1 S 0 ) feeding a 2:1 MUX (select S 2 ).
Multiplexer n:1 digital switch
Universal function generator