Edge-triggered D flip-flop

WHAT is it?

The subscript matters: $Q_{n+1}$ is the state after the edge, computed from $D$ sampled at the edge.

HOW is it built? (Derivation from scratch)

We build it in three layers, each solving a flaw in the previous.

Layer 1 — the SR latch (feedback = memory)

Cross-couple two NOR gates:

$Q = \overline{R + \overline{Q}}, \qquad \overline{Q} = \overline{S + Q}$

$S=1,R=0 \Rightarrow Q=1$ (Set)
$S=0,R=1 \Rightarrow Q=0$ (Reset)
$S=R=0 \Rightarrow$ hold (feedback keeps last value) → this is the memory.
$S=R=1 \Rightarrow$ forbidden.

Layer 2 — gated D latch (remove the forbidden state)

Force $S$ and $R$ to be opposites and gate them with an Enable: $S = D\cdot E,\qquad R=\overline{D}\cdot E$ When $E=1$ : $S=D,\ R=\overline{D}$ → $Q=D$ (transparent). When $E=0$ : $S=R=0$ → hold. The forbidden state can never occur because $S,R$ are complementary. But it is still level-triggered.

Layer 3 — master–slave = edge behaviour

Chain two D latches with opposite enables:

Master latch enabled by $\overline{CLK}$
Slave latch enabled by $CLK$

Trace a rising edge:

While $CLK=0$ : master is transparent (tracks $D$ ), slave is closed (holds old $Q$ ).
At the rising edge $CLK:0\to1$ : master freezes the value it had just before the edge; slave opens and copies that frozen value to $Q$ .
While $CLK=1$ : master closed (ignores new $D$ ), slave transparent but its input (master output) is frozen → $Q$ stable.

Result: $Q$ changes once, at the edge, to whatever $D$ was just before the edge. That is exactly edge-triggering. 🎉

Timing: the numbers that make it real

Worked examples

Flashcards

What distinguishes edge-triggered from level-triggered storage?

Edge-triggered (flip-flop) updates output only at a clock edge; level-triggered (latch) is transparent for a whole clock level.

Characteristic equation of a D flip-flop

Q_{n+1}=D

(next state = sampled input, independent of

Q_n

Why chain two latches with opposite enables (master–slave)?

So exactly one is open at a time; the value is frozen at the edge, giving edge-triggered (non-transparent) behaviour.

Define setup time.

Minimum time D must be stable before the active clock edge to be captured reliably.

Define hold time.

Minimum time D must remain stable after the edge.

What is metastability?

An unstable state where Q hovers between 0 and 1, caused by violating setup/hold; resolves after unpredictable delay.

Formula for max clock frequency of a FF→logic→FF path

f_{max}=1/(t_{cq}+t_{comb}+t_{su})

How to make a D flip-flop toggle (÷2)?

Connect

\overline{Q}

back to

D

; each edge inverts Q.

Why does edge-triggering enable safe shift registers?

The edge closes the input almost instantly, so data hops exactly one stage per clock instead of racing through.

What clock event triggers a positive-edge FF?

The rising (0→1) transition of the clock.

Recall Feynman: explain to a 12-year-old

Imagine a mailbox with a flap that snaps shut. A postman (the clock) walks past once every tick. At the exact moment he passes, whatever letter (D) is in your hand goes into the box — and the flap slams. For the rest of the time the box is locked: you can wave any letter around, nothing changes. When the postman comes again, the box swaps to your new letter. That "snap at the passing moment" is the edge. That's why the whole computer stays neat: everyone's mailbox updates together, once per tick.

Connections

SR latch — the bistable core (memory via feedback)
Gated D latch — removes forbidden state, still level-triggered
Master-slave configuration — how the edge is achieved
JK flip-flop / T flip-flop — richer characteristic equations
Setup and hold time & Metastability — timing correctness
Registers and shift registers — many D-FFs sharing a clock
Synchronous counters — built from toggling D/T flip-flops
Clock distribution and skew — why one edge for everyone matters

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, D flip-flop ek chhota sa 1-bit memory cell hai. Iska kaam simple hai: jab clock ka edge aata hai (positive-edge device me rising edge, yaani 0 se 1), tab wo input $D$ ki value ko copy karke $Q$ me daal deta hai — $Q_{n+1}=D$ . Baaki poore time, chahe clock high rahe ya low, $D$ bhale hi hilta rahe, output freeze rehta hai. Isiliye ise "edge-triggered" bolte hain — sirf edge ke instant pe photo click hoti hai, bas.

Ab confusion yahin hoti hai: latch aur flip-flop same nahi hain. Latch level-triggered hota hai — jab tak enable high hai, $Q$ transparently $D$ ko follow karta rehta hai. Flip-flop edge pe lock kar deta hai. Yeh farak bahut important hai, kyunki agar shift register me sab latch transparent ho jayein toh data ek hi clock phase me saare stages ko cross kar jayega (race condition). Edge-triggering "ek tick me ek hop" guarantee karta hai. Isliye pura synchronous computer ek hi heartbeat pe chalta hai.

Banane ka tareeka: pehle SR latch (feedback = memory), phir gated D latch (forbidden state hata do, $S=D,R=\overline D$ ), phir do latch ulta enable ke saath jodo — master-slave. Master $\overline{CLK}$ pe khulta, slave $CLK$ pe. Edge ke waqt master freeze, slave open — bas edge behaviour mil gaya. Yaad rakho "master sote hai jab slave kaam karta hai".

Timing bhi dhyaan rakho: $D$ ko edge se pehle setup time aur baad me hold time tak stable rehna chahiye, warna FF metastable ho jayega (0 aur 1 ke beech latak jayega). Aur max frequency nikalti hai $f_{max}=1/(t_{cq}+t_{comb}+t_{su})$ se — kyunki ek clock period me data ko ek FF se nikalna, logic paar karna, aur agle FF ka setup satisfy karna, sab hona chahiye.

WHAT is it?

WHY do we need the edge?

HOW is it built? (Derivation from scratch)

Layer 1 — the SR latch (feedback = memory)

Layer 2 — gated D latch (remove the forbidden state)

Layer 3 — master–slave = edge behaviour

Timing: the numbers that make it real

Worked examples

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Sequential Circuits

Connections