Edge-triggered D flip-flop: Exercises — Hardware deep dive

Before we start, three symbols we will lean on constantly:

The timing exercises (Levels 2, 3, 5) need four more symbols. Here they are once, up front, in plain words — every later use refers back to these:

Level 1 — Recognition

L1.1 — Which one can change right now?

Two boxes both store one bit. Box A is transparent while its enable is high; Box B changes only at the rising edge. It is the middle of a clock's high level and $D$ just flipped from 0 to 1. Which box's output can change this instant?

Recall Solution

Box A (the latch).

What decides: ask "when is the door open?"
Box A is a level-triggered latch: while enable is high it is transparent, so a change in $D$ passes straight to its output — even mid-level. So Box A's output can change now.
Box B is the edge-triggered flip-flop: it only samples $D$ at the rising edge. We are in the middle of the high level, not at an edge, so Box B ignores the flip. Its output stays put. Answer: Box A can change; Box B cannot.

L1.2 — Read one edge

A positive-edge D flip-flop currently outputs $Q_{n} = 0$ . At the next rising edge, $D = 1$ . What is $Q_{n + 1}$ ?

Recall Solution

Use the characteristic equation $Q_{n + 1} = D$ . The old value $Q_{n}$ does not matter for a D flip-flop — it just loads $D$ . $Q_{n + 1} = D = 1.$ Answer: $Q_{n + 1} = 1$ .

L1.3 — Name the trigger

For a positive-edge device, exactly which clock event copies $D$ into $Q$ : the high level, the low level, the rising edge, or the falling edge?

Recall Solution

The rising edge — the $0 \to 1$ transition. "Positive edge" means the upward transition. During the high or low level, and at the falling edge, $Q$ is frozen. Answer: the rising ( $0 \to 1$ ) edge.

Level 2 — Application

L2.1 — Read a whole waveform

Positive-edge FF, starting at $Q = 0$ . Rising edges occur at $t = 1, 2, 3, 4, 5$ . The input is: $D = 1$ at $t = 1$ ; $D = 1$ at $t = 2$ ; $D = 0$ at $t = 3$ ; $D = 0$ at $t = 4$ ; $D = 1$ at $t = 5$ . (Between edges $D$ may wiggle — ignore it.) Give $Q$ after each edge.

Figure L2.1 — Three stacked chalk waveforms: blue $C L K$ (top) with arrows marking the five rising edges at $t = 1 \dots 5$ ; yellow $D$ (middle); pink $Q$ (bottom). $Q$ is a staircase that only steps at a dotted edge line, each time jumping to the height $D$ has at that edge — visually confirming $Q$ copies $D$ only at edges and holds flat in between.

Recall Solution

Apply $Q_{n + 1} = D$ at each edge; hold in between.

edge $t$	$D$ sampled	$Q$ after
1	1	1
2	1	1
3	0	0
4	0	0
5	1	1
What it looks like (figure): $Q$ is a "staircase" that only ever steps at a dotted edge line, copying $D$ 's height there.
Answer sequence: $1, 1, 0, 0, 1$ .

L2.2 — Toggle wiring (divide-by-2)

You connect $\overline{Q}$ back into $D$ (so $D = \overline{Q}$ always). Start $Q = 0$ . Write $Q$ after edges 1,2,3,4.

Recall Solution

Since $D = \overline{Q}$ , the characteristic equation becomes $Q_{n + 1} = \overline{Q_{n}}$ — each edge inverts the output.

Start $Q = 0$ .
Edge 1: $D = \overline{0} = 1$ sampled → $Q = 1$ .
Edge 2: $D = \overline{1} = 0$ → $Q = 0$ .
Edge 3: $Q = 1$ .
Edge 4: $Q = 0$ . The output completes one full cycle ( $0 \to 1 \to 0$ ) every two clock edges, so its frequency is half the clock's — a divide-by-2. Answer: $1, 0, 1, 0$ .

L2.3 — Max clock frequency

A single FF→logic→FF path has $t_{c q} = 3$ ns (clock-to-Q delay), $t_{co mb} = 5$ ns (logic delay), $t_{s u} = 2$ ns (setup time). Find the minimum clock period $T_{min}$ and the maximum frequency $f_{ma x}$ . (All four timing symbols were defined up front; here we use three of them.)

Recall Solution

All three delays happen in series inside one clock period: the edge fires ( $t_{c q}$ ), data crawls through logic ( $t_{co mb}$ ), then must be steady before the next edge ( $t_{s u}$ ). $T_{min} = t_{c q} + t_{co mb} + t_{s u} = 3 + 5 + 2 = 10 ns .$ $f_{ma x} = \frac{1}{T _{min}} = \frac{1}{10 ns} = 100 MHz .$ Answer: $T_{min} = 10$ ns, $f_{ma x} = 100$ MHz.

Level 3 — Analysis

L3.1 — Setup/hold keep-out window

Recall from the timing definitions up front: setup time $t_{s u}$ = how long $D$ must be stable before the edge; hold time $t_{h}$ = how long $D$ must stay stable after the edge. Here $t_{s u} = 2$ ns and $t_{h} = 1$ ns, and a rising edge occurs at $t = 20$ ns. State the exact time interval during which $D$ must not change. If $D$ changes at $t = 19.5$ ns, is that legal?

Figure L3.1 — A chalk timeline: the blue clock edge stands at $t = 20$ ns. A pink shaded band stretches from $t = 18$ ns (one setup time $t_{s u} = 2$ ns to the left of the edge) to $t = 21$ ns (one hold time $t_{h} = 1$ ns to the right). Inside this band $D$ must stay flat. A yellow marker at $t = 19.5$ ns sits inside the band, showing the illegal change that risks metastability.

Recall Solution

Setup ( $t_{s u} = 2$ ns) means $D$ must be stable before the edge → from $t = 20 - 2 = 18$ ns.
Hold ( $t_{h} = 1$ ns) means $D$ must stay stable after the edge → until $t = 20 + 1 = 21$ ns.
Keep-out window = $[20 - 2, 20 + 1] = [18 ns, 21 ns]$ . A change at $t = 19.5$ ns is inside this window → illegal. It risks pushing the FF into metastability (see Metastability), where $Q$ hovers between 0 and 1. Answer: forbidden interval $[18, 21]$ ns; the $t = 19.5$ ns change is illegal.

L3.2 — Latch chain race vs. flip-flop chain

Three storage stages are chained: output of stage 1 → input of stage 2 → input of stage 3, all sharing one clock. Case A: all three are transparent latches. Case B: all three are edge-triggered flip-flops. During a single clock's high level, how many stages can a brand-new value at stage 1's input reach in Case A vs Case B?

Recall Solution

Case A (latches): while the clock is high, all three latches are transparent — the door is open on every stage at once. A new value at stage 1 races through all three in one high phase. You lose control of "one hop per clock". This is the transparency problem. Case B (flip-flops): each FF samples only at the edge and then locks. At one edge, stage 1 captures the new input; stage 2 captures whatever stage 1 held before this edge; stage 3 likewise. So the value moves exactly one stage per edge. Answer: Case A → all 3 (race); Case B → exactly 1. This is why Registers and shift registers use flip-flops.

L3.3 — Master–slave state at each moment

In a master–slave FF the master latch is enabled by $\overline{C L K}$ and the slave by $C L K$ . For each of these moments, say which latch is open (transparent) and which is closed (holding): (a) $C L K = 0$ , (b) exactly at rising edge $C L K : 0 \to 1$ , (c) $C L K = 1$ .

Recall Solution

Opposite enables mean exactly one is ever open.

(a) $C L K = 0$ : $\overline{C L K} = 1$ → master open (tracks $D$ ), slave closed (holds old $Q$ ).
(b) rising edge: $\overline{C L K}$ falls, master snaps shut freezing the value it just held; $C L K$ rises, slave opens and copies that frozen value to $Q$ . This handover is the edge event.
(c) $C L K = 1$ : master closed (ignores new $D$ ), slave open but its input (master output) is frozen, so $Q$ is stable. Answer: master open at $C L K = 0$ ; handover at the edge; slave open (but fed a frozen value) at $C L K = 1$ . See Master-slave configuration.

Level 4 — Synthesis

L4.1 — Build a T (toggle) flip-flop from a D-FF

First, one piece of notation: $\oplus$ is the exclusive-OR (XOR) operation. $A \oplus B$ equals 1 when the two bits differ, and 0 when they are the same. In words: "output 1 if exactly one input is 1." (So $0 \oplus 0 = 0$ , $0 \oplus 1 = 1$ , $1 \oplus 0 = 1$ , $1 \oplus 1 = 0$ .) It is the natural "toggle detector": XOR-ing a bit with 1 flips it, XOR-ing with 0 leaves it.

Now design logic so a D flip-flop behaves like a T flip-flop: when control input $T = 1$ it toggles on each edge, when $T = 0$ it holds. Give the equation for $D$ in terms of $T$ and $Q_{n}$ , and verify all four rows.

Recall Solution

A T flip-flop's target behaviour: $Q_{n + 1} = T \oplus Q_{n}$ (using $\oplus$ = XOR defined above: toggle when $T = 1$ , hold when $T = 0$ ). Since a D-FF just loads $D$ (i.e. $Q_{n + 1} = D$ ), we must feed that target into $D$ : $D = T \oplus Q_{n} = T \overline{Q_{n}} + \overline{T} Q_{n}$ (Recall: the overline means NOT, so $\overline{Q_{n}}$ and $\overline{T}$ are the flipped bits.) Wire an XOR gate: inputs $T$ and current $Q$ ; output → $D$ . Verify:

$T$	$Q_{n}$	$D = T \oplus Q_{n}$	$Q_{n + 1}$
0	0	0	0 (hold)
0	1	1	1 (hold)
1	0	1	1 (toggle)
1	1	0	0 (toggle)
Every row matches the desired T behaviour. See T flip-flop.
Answer: $D = T \oplus Q_{n}$ .

L4.2 — Build a JK from a D-FF

A JK flip-flop obeys $Q_{n + 1} = J \overline{Q_{n}} + \overline{K} Q_{n}$ (the overlines are logical NOT, as defined up front). Realise it using a D flip-flop plus gates: give the expression for $D$ .

Recall Solution

Again, whatever we want $Q_{n + 1}$ to be, we simply drive onto $D$ (because $Q_{n + 1} = D$ ): $D = J \overline{Q_{n}} + \overline{K} Q_{n}$ Check the four JK cases:

$J = 0, K = 0$ : $D = Q_{n}$ → hold ✓
$J = 0, K = 1$ : $D = 0$ → reset ✓
$J = 1, K = 0$ : $D = \overline{Q_{n}} \cdot 1 + 1 \cdot Q_{n} = 1$ → set ✓
$J = 1, K = 1$ : $D = \overline{Q_{n}}$ → toggle ✓ All four JK modes reproduced. See JK flip-flop. Answer: $D = J \overline{Q_{n}} + \overline{K} Q_{n}$ .

L4.3 — Two-bit shift register output

Two positive-edge D-FFs chained: $D_{0} = X$ (external input), $D_{1} = Q_{0}$ . Both start at 0. The input stream on $X$ (sampled at edges 1..4) is $1, 0, 1, 1$ . Give $(Q_{0}, Q_{1})$ after each of the four edges.

Recall Solution

At every edge: $Q_{0} \leftarrow X$ (the input at that edge), and $Q_{1} \leftarrow Q_{0}$ (the value $Q_{0}$ held just before the edge). Order matters — both use pre-edge values, captured simultaneously.

edge	$X$	old $Q_{0}$	new $Q_{0} = X$	new $Q_{1} =$ old $Q_{0}$
1	1	0	1	0
2	0	1	0	1
3	1	0	1	0
4	1	1	1	1
So $(Q_{0}, Q_{1})$ = $(1, 0), (0, 1), (1, 0), (1, 1)$ . The bit entered at edge 1 appears at $Q_{1}$ one edge later — the classic one-hop-per-clock delay.
Answer: $(1, 0), (0, 1), (1, 0), (1, 1)$ .

Level 5 — Mastery

L5.1 — Pipeline retiming for speed

A path has $t_{c q} = 2$ ns, $t_{s u} = 1$ ns, and a block of combinational logic taking $t_{co mb} = 12$ ns. First find $f_{ma x}$ . Then you split the logic into two equal halves ( $6$ ns each) and insert a flip-flop between them (a pipeline register). Find the new $f_{ma x}$ . By what factor did throughput improve?

Recall Solution

Before: one big path. $T_{min} = t_{c q} + t_{co mb} + t_{s u} = 2 + 12 + 1 = 15 ns \Rightarrow f_{ma x} = \frac{1}{15 ns} \approx 66.7 MHz .$ After pipelining: the worst stage now spans one FF, $6$ ns of logic, and the next FF: $T_{min}^{'} = t_{c q} + \frac{t _{co mb}}{2} + t_{s u} = 2 + 6 + 1 = 9 ns \Rightarrow f_{ma x}^{'} = \frac{1}{9 ns} \approx 111 MHz .$ Speed-up factor: $\frac{15}{9} = 1. \overline{6} \approx 1.67 \times$ . Why less than $2 \times$ : each stage still pays the fixed overhead $t_{c q} + t_{s u} = 2 + 1 = 3 ns$ that does not shrink when you halve the logic. Only the $t_{co mb}$ part gets divided; the $3$ ns of overhead is paid once per stage regardless. If overhead were zero the period would drop from $12$ ns to $6$ ns — a full $2 \times$ — but the stubborn $3$ ns caps the real gain at $15/9 \approx 1.67 \times$ . Takeaway: pipelining's payoff is limited by the per-stage $t_{c q} + t_{s u}$ overhead. See Synchronous counters and clocking in Registers and shift registers. Answer: $66.7$ MHz → $111$ MHz, about $1.67 \times$ faster.

L5.2 — Clock skew eats your margin

Two flip-flops share a clock, but the wire to the receiving FF is longer, so its edge arrives $t_{s k e w} = 2$ ns later than the sender's. Path values: $t_{c q} = 2$ ns, $t_{co mb} = 5$ ns, $t_{s u} = 1$ ns. The skew adds time to the receiver's deadline, so the setup constraint becomes $T_{c l k} + t_{s k e w} \geq t_{c q} + t_{co mb} + t_{s u}$ . Find the new minimum period and compare to the zero-skew case.

Recall Solution

Zero-skew baseline: $T_{min} = 2 + 5 + 1 = 8$ ns. With late receiver clock: the receiver's edge arrives $t_{s k e w}$ later, effectively lengthening the allowed period: $T_{c l k} \geq (t_{c q} + t_{co mb} + t_{s u}) - t_{s k e w} = 8 - 2 = 6 ns .$ So this particular skew direction helps the setup path (period can be as low as $6$ ns). But beware — the same skew hurts the hold constraint (data can arrive too early at the receiver's now-later edge), which is why real designers treat skew as dangerous. See Clock distribution and skew. Answer: setup allows $T_{min} = 6$ ns (vs $8$ ns) — but this skew direction jeopardises hold time.

L5.3 — Metastability probability intuition

A D-FF that just went metastable resolves toward a valid 0/1 with the probability of still being stuck decaying exponentially with waiting time $t$ : $P (t) = e^{- t / τ}$ , with time constant $τ = 0.5$ ns. How long must you wait so the chance of remaining metastable is below $1 \times 1 0^{- 6}$ ?

Recall Solution

Why exponential: metastability resolution is a memoryless escape from an unstable balance point — like a pencil balanced on its tip, the longer it survives the rarer that becomes, at a constant fractional rate. That constant-rate decay is exactly $e^{- t / τ}$ . Set $e^{- t / τ} < 1 0^{- 6}$ . Take natural log (which undoes $e^{x}$ ): $- \frac{t}{τ} < ln (1 0^{- 6}) = - 6 ln 10 \Rightarrow t > τ \cdot 6 ln 10.$ $t > 0.5 \times 6 \times 2.302585 = 0.5 \times 13.8155 = 6.9078 ns .$ So wait about $6.91$ ns (roughly $14 τ$ ). See Metastability. Answer: $t \approx 6.91$ ns.

Recall Self-test recap (cover the answers)

D flip-flop characteristic equation ::: $Q_{n + 1} = D$ To toggle a D-FF, set $D =$ ::: $\overline{Q_{n}}$ (or $T \oplus Q_{n}$ for a T-FF) Keep-out window around an edge at $t_{e}$ ::: $[t_{e} - t_{s u}, t_{e} + t_{h}]$ $f_{ma x}$ of one FF→logic→FF path ::: $1/ (t_{c q} + t_{co mb} + t_{s u})$ In a shift register, $Q_{1}$ receives the old or new? $Q_{0}$ at each edge ::: the old (pre-edge) value

Connections

Parent: Edge-triggered D flip-flop
SR latch · Gated D latch · Master-slave configuration — the build layers used in L3.3
T flip-flop · JK flip-flop — synthesised from a D-FF in L4
Setup and hold time · Metastability — timing correctness (L3, L5)
Registers and shift registers · Synchronous counters — L3.2, L4.3, L5.1
Clock distribution and skew — L5.2